MCD212 Datasheet, PDF (22/87 Pages) Motorola, Inc – Video Decoder and System Controller(with JTAG)

3.5
ADDRESS DECODING
The VDSC is connected to the system bus via 22 address lines and upper and lower data strobes. The
address decoding is validated by CS.
Table 3–1. Address Map
h000000 – h3FFFFF
h400000 – h4FFBFF
h4FFC00 – h4FFFDF
DRAM (4M byte)
System ROM (1M byte)
System I/O (1K byte)
h4FFFE0 – h4FFFEF
h4FFFF0 – h4FFFFF
Channel 2 internal registers
Channel 1 internal registers
NOTE:The system ROM decoding asserts the CSROM pin that is not
sensitive to the R/W signal. This allows the use of static RAM in
the ROM mapping area. The system I/O decoding asserts the
CSIO pin.
3.6
DATA ACKNOWLEDGE GENERATION
A data transfer is initiated by an upper and/or lower data strobe (U/LDS) from the system. A data
transfer is acknowledged by the VDSC via DTACK. A data transfer is terminated by U/LDS becoming
inactive followed by DTACK becoming inactive.
The VDSC generates the data acknowledge (DTACK) depending on the addressed area:
• Access to the DRAM is acknowledged as soon as it is certain that data can be read or written by the
system.
• Access to the system ROM is acknowledged after a programmable number of clock or CLK cycles. The
DTACK delay is controlled by Control Register CSR1W.
If U/LDS becomes inactive before DTACK is generated by the VDSC, DTACK will not be generated.
Table 3–2. DTACK Delay for ROM
DD
DD1 DD2 CLK Cycles
0
x
x
11 ≥ 12
1
0
0
3≥4
1
0
1
5≥6
1
1
0
7≥8
1
1
1
9 ≥ 10
NOTE: Access to the SYSTEM I/O device (CSIO
pin) is not acknowledged by the VDSC
but by the addressed device.
MOTOROLA
MCD212
3–3