56F8356 Datasheet, PDF (34/160 Pages) Motorola, Inc – 56F8356 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
Part 4 Memory Operating Modes (MEM)
4.1 Introduction
The 56F8356 device is a 16-bit motor-control chip based on the 56800E core. It uses a
Harvard-style architecture with two independent memory spaces for Data and Program. On-chip
RAM and Flash memories are used in both spaces.
This section provides memory maps for:
• Program Address Space, including the Interrupt Vector Table
• Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for each device are summarized in Table 4-1. Flash memories’ restrictions
are identified in the “Use Restrictions” column of Table 4-1.
On-Chip Memory
Program Flash
Data Flash
Program RAM
Data RAM
Program Boot Flash
Table 4-1 Chip Memory Configurations
56F8356
Use Restrictions
256KB
Erase / Program via Flash interface unit and word writes to CDBW
8KB
Erase / Program via Flash interface unit and word writes to CDBW. Data
Flash can be read via either CDBR or XDB2, but not by both simultaneously
4KB
None
16KB
None
16KB
Erase / Program via Flash Interface unit and word to CDBW
34
56F8356 Technical Data
For More Information On This Product,
Preliminary
Go to: www.freescale.com