56F8356 Datasheet, PDF (112/160 Pages) Motorola, Inc – 56F8356 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the
peripheral and system (core and memory) clocks. The maximum master clock frequency is
120MHz. Peripheral and system clocks are generated at half the master clock frequency and
therefore at a maximum 60MHz. The SIM provides power modes (Stop, Wait) and clock enables
(SIM_PCE register, CLK_DIS, ONCE_EBL) to control which clocks are in operation. The OCCS,
power modes, and clock enables provide a flexible means to manage power consumption.
Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may
be shut down when not in use. When the PLL is in use, its prescaler and postscaler can be used to
limit PLL and master clock frequency. Power modes permit system and/or peripheral clocks to be
disabled when unused. Clock enables provide the means to disable individual clocks. Some
peripherals provide further controls to disable unused subfunctions. Refer to the Part 3, On-Chip
Clock Synthesis (OCCS) and the 56F8300 Peripheral User Manual for further details.
6.7 Power-Down Modes Overview
The 56F8356 operates in one of three power-down modes, as shown in Table 6-3.
Table 6-3 Clock Operation in Power-Down Modes
Mode
Core Clocks
Peripheral Clocks
Description
Run
Wait
Stop
Active
Active
Device is fully functional
Core and memory Active
clocks disabled
Peripherals are active and can product interrupts if they
have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
System clocks continue to be generated in
the SIM, but most are gated prior to
reaching memory, core and peripherals.
The only possible recoveries from Stop mode are:
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts
3. COP reset
4. External reset
5. Power-on reset
All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the
same as the main processor frequency in this architecture. The maximum frequency of operation
is SYS_CLK = 60MHz.
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