56F8356 Datasheet, PDF (111/160 Pages) Motorola, Inc – 56F8356 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
Register Descriptions
“Hard Coded” Address Portion ^{Instruction Portion}
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_ISALL Register
2 bits from SIM_ISALH Register
Full 24-Bit for Short I/O Address
Figure 6-13 I/O Short Address Determination
With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its
peripheral registers and then use the I/O Short addressing mode to reference them. The ISR should
restore this register to its previous contents prior to returning from interrupt.
Note: The default value of this register set points to the EOnCE registers.
Note:
The pipeline delay between setting this register set and using short I/O addressing with the
new value is three cycles.
Base + $D 15 14 13 12 11 10 9
8
7
6
5
4
3
Read
1
1
1
1
1
1
1
1
1
1
1
1
1
Write
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
2
10
1
ISAL[23:22]
1
1
1
Figure 6-14 I/O Short Address Location High Register (SIM_ISALH)
6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0
This field represents the upper two address bits of the “hard coded” I/O short address.
Base + $E _{15 14 13 12 11 10 9}
8
7
6
5
4
3
Read
Write
ISAL[21:6]
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
2
10
1
1
1
Figure 6-15 I/O Short Address Location Low Register (SIM_ISALL)
6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
56F8356 Technical Data
111
Preliminary
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