MC68HCP11 Datasheet, PDF (21/45 Pages) Motorola, Inc – 8-Bit Microcontroller

Simple
strobed
mode
STAF
Clearing
Sequence
Read PIOC
with STAF=1
then read
PORTCL
HNDS
0
Table 5 Parallel I/O Control
OIN
PLS
X
X
EGA
0
1
Full input Read PIOC
1
handshake with STAF=1
then read
PORTCL
0 0 = STRB
active level
1
1 = STRB
active pulse
0
Full output Read PIOC
1
handshake with STAF=1
then write to
PORTCL
1 0 = STRB
active level
1 = STRB
active pulse
0
Port C
1
Driven
STRA
Follow ^{Active Edge} Follow
DDRC
DDRC
Port C
Port B
Inputs latched
into PORTCL
on any active
edge on STRA
STRB
pulses on
writes to
port B
Inputs latched Normal out-
into PORTCL put port,
on any active unaffected
edge on STRA in hand-
shake
modes
Driven as out- Normal out-
puts if STRA at put port,
active level, unaffected
follows DDRC in hand-
if STRA not at shake
active level
modes
PORTC — Port C Data
$1003
Bit 7
6
5
4
3
2
1
Bit 0
PC7
S. Chip
or Boot: PC7
RESET:
0
Expan. or ADDR7/
Test: DATA7
PC6
PC6
0
ADDR6/
DATA6
PC5
PC5
0
ADDR5/
DATA5
PC4
PC4
0
ADDR4/
DATA4
PC3
PC3
0
ADDR3/
DATA3
PC2
PC2
0
ADDR2/
DATA2
PC1
PC1
0
ADDR1/
DATA1
PC0
PC0
0
ADDR0/
DATA0
NOTE
In single chip and boot modes, port C pins reset to high impedance inputs (DDRC
registers are set to zero). In expanded and special test modes, port C is a multi-
plexed address/data bus and the port C register address is treated as an external
memory location.
PORTB — Port B Data
$1004
Bit 7
6
5
4
3
2
1
Bit 0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
S. Chip
or Boot: PB7
PB6
PB5
PB4
PB3
PB2
RESET:
0
0
0
0
0
0
Expan. or
Test: ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10
PB1
0
ADDR9
PB0
0
ADDR8
PORTCL — Port C Latched
$1005
RESET:
Bit 7
PCL7
U
6
PCL6
U
5
PCL5
U
4
PCL4
U
3
PCL3
U
2
PCL2
U
1
PCL1
U
Bit 0
PCL0
U
Writes affect port C pins. PORTCL is used in the handshake clearing mechanism. When an active edge
occurs on the STRA pin, port C data is latched into the PORTCL register.
MC68HC11A8
MC68HC11A8TS/D
MOTOROLA
21