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MC68HCP11 Datasheet, PDF (15/45 Pages) Motorola, Inc – 8-Bit Microcontroller | |||
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DLY â Enable Oscillator Start-Up Delay on Exit from STOP
0 = No stabilization delay on exit from STOP
1 = Stabilization delay enabled on exit from STOP
CME â Clock Monitor Enable
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset
CR1, CR0 â COP Timer Rate Select
CR [1:0]
00
01
10
11
Divide
E/215
By
1
4
16
64
E=
XTAL = 4.0 Mhz
Timeout
â0/+32.8 ms
32.768 ms
131.072 ms
524.288 ms
2.097 sec
1.0 MHz
XTAL = 8.0 MHz
Timeout
â0/+16.4 ms
16.384 ms
65.536 ms
262.140 ms
1.049 sec
2.0 MHz
XTAL = 12.0 MHz
Timeout
â0/+10.9 ms
10.923 ms
43.691 ms
174.76 ms
699.05 ms
3.0 MHz
COPRST â Arm/Reset COP Timer Circuitry
$103A
Bit 7
6
5
4
3
2
1
Bit 0
7
6
5
4
3
2
1
0
RESET:
0
0
0
0
0
0
0
0
Write $55 to COPRST to arm COP watchdog clearing mechanism. Write $AA to COPRST to reset COP
watchdog.
HPRIO â Highest Priority I-Bit Interrupt and Miscellaneous
RESET:
Bit 7
RBOOT
â
6
SMOD
â
5
MDA
â
4
3
2
IRV PSEL3 PSEL2
â
0
1
$103C
1
PSEL1
0
Bit 0
PSEL0
1
RBOOT â Read Bootstrap ROM Bits 7â4
Refer to 2 Operating Modes and Memory Maps.
SMOD â Special Mode Select
Refer to 2 Operating Modes and Memory Maps.
MDA â Mode Select A
Refer to 2 Operating Modes and Memory Maps.
IRV â Internal Read Visibility
Refer to 2 Operating Modes and Memory Maps.
PSEL[3:0] â Priority Select Bits 3 through 0
Can be written only while the I bit in the CCR is set (interrupts disabled). These bits select one interrupt
source to be elevated above all other I-bit related sources.
MC68HC11A8
MC68HC11A8TS/D
MOTOROLA
15
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