MC68HCP11 Datasheet, PDF (11/45 Pages) Motorola, Inc – 8-Bit Microcontroller

HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous
$103C
RESET:
Bit 7
RBOOT
—
6
SMOD
—
5
MDA
—
4
3
2
1
Bit 0
IRV PSEL3 PSEL2 PSEL1 PSEL0
—
0
1
0
1
RBOOT, SMOD, and MDA reset depend on conditions at reset and can only be written in special modes
(SMOD = 1).
RBOOT — Read Bootstrap ROM
0 = Bootloader ROM disabled and not in map
1 = Bootloader ROM enabled and in map at $BF40–$BFFF
SMOD —Special Mode Select
MDA — Mode Select A
Inputs
MODB
1
1
0
0
MODA
0
1
0
1
Mode
Single Chip
Expanded Multiplexed
Special Bootstrap
Special Test
Latched at Reset
RBOOT
SMOD
MDA
0
0
0
0
0
1
1
1
0
0
1
1
IRV — Internal Read Visibility
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out through the external data bus
PSEL3–PSEL0 — Priority Select Bits 3 through 0
Refer to 3 Resets and Interrupts.
INIT — RAM and I/O Mapping
RESET:
Bit 7
RAM3
0
6
RAM2
0
5
RAM1
0
4
RAM0
0
3
REG3
0
2
REG2
0
$103D
1
REG1
0
Bit 0
REG0
1
RAM[3:0] —256-Byte Internal RAM Map Position
RAM[3:0] determine the upper four bits of the RAM address, positioning RAM at the selected 4K bound-
ary.
REG[3:0] —64-Byte Register Block Map Position
REG[3:0] determine the upper four bits of the register address, positioning registers at the selected 4K
boundary. Register can be written only once in the first 64 cycles out of reset in normal modes, or any
time in special modes.
MC68HC11A8
MC68HC11A8TS/D
MOTOROLA
11