33702 Datasheet, PDF (16/24 Pages) Motorola, Inc – 3.0 A Switch-Mode Power Supply with Linear Regulator

Freescale Semiconductor, Inc.
∆V = 2.0 V
Max. Lead
V Start-Up
5.0 V Input Supply
3.3 V I/O Voltage (V_OUT)
1.8 V Core Voltage(VLDO)
∆V = 0.4 V
Max. Lag
∆V = 0.4 V
Max. Lag
∆V = 2.0 V
Max. Lead
Figure 12. Inverted Power Up/Down Sequence in +5.0 V
Supply System
Standard Power Sequencing
When the power supply IC operates in the Standard Power
Sequencing mode, the switcher output provides the core
voltage for the microprocessor. This situation and operating
conditions are illustrated in Figure 10 and Figure 11. Table 2,
page 15, shows the Power Sequencing mode selection.
Inverted Power Sequencing
When the power supply IC is operating in the Inverted Power
Sequencing mode, the linear regulator (LDO) output provides
the core voltage for the microprocessor, as illustrated in
Figure 12. Table 2 shows the Power Sequencing mode
selection.
33702 POWER SEQUENCING
Requirements
1. I/O supply voltage not to exceed core voltage by more than
2.0 V.
2. Core supply voltage not to exceed I/O voltage by more
than 0.4 V.
Methods of Control
The 33702 has several methods of monitoring and
controlling the regulator output voltages, as described in the
paragraphs below. Power sequencing control is also achieved
through the intrinsic operation of the regulators. The EN1 and
EN2 pins can be used to disable the power sequencing (refer to
Table 2, page 15.
Intrinsic Operation
For both the LDO and switcher, whenever the output voltage
is below the regulation point, the LDO external Pass FET will be
on or the Buck High-Side FET will be on at a duty cycle
controlled by the switcher. Because these devices are FETs,
current can flow in either direction, balancing the voltages via
the common supply pin. The ability to maintain the FETs on will
depend on the available gate voltage, and thus the size of the
boost regulator storage capacitor.
Standard Power Sequencing Control
Comparators monitor voltage differences between the LDO
(LDO pin) and the switcher (V_OUT pin) outputs as follows:
1. LDO > V_OUT + 1.8 V, turn off LDO. The LDO can be
forced off. This occurs whenever the LDO output voltage
exceeds the switcher output voltage by more than 1.8 V.
2. LDO > V_OUT + 1.9 V, shunt LDO to ground. If turning off
the LDO is insufficient and the LDO output voltage
exceeds the switcher output voltage by more than 1.9 V,
a 1.0 Ω shunt FET is turned on that discharges the LDO
load capacitor to ground. The shunt FET is used for
switcher output shorts to ground and for power down in
case of V_IN1 ≠ V_IN2 with the switcher output falling faster
than the LDO.
3. LDO < V_OUT + 1.7 V, cancel (1) and (2) above, re-enable
LDO. Normal operation resumes when the LDO output
voltage is less than 1.7 V above the switcher output
voltage.
4. LDO < V_OUT - 0.2 V, turn off switcher. The switcher can
be forced off. This occurs whenever the LDO is less than
V_OUT - 0.2 V.
5. LDO < V_OUT - 0.3 V, turn on Sync (LS) FET and 1.0 Ω
V_OUT sink FET. The Buck High-Side FET is forced off and
the Sync FET is forced on. This occurs when the switcher
output voltage exceeds the LDO output by more than
300 mV.
6. LDO > V_OUT , reset (4) and (5) above. Normal operation
resumes when LDO > V_OUT.
33702
16
For More Information O^Mn^OTT^Oh^Ri^Os^LP^Ar^Ao^Nd^Au^LOc^Gt,^{INTEGRATED CIRCUIT DEVICE DATA}
Go to: www.freescale.com