33702 Datasheet, PDF (11/24 Pages) Motorola, Inc – 3.0 A Switch-Mode Power Supply with Linear Regulator

Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40°C ≤ T_J ≤ 125°C unless otherwise noted. Input voltages V_IN1 = V_IN2 = 3.3 V using the typical
application circuit (see Figure 20) unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LINEAR REGULATOR (LDO)
LDO Output Current Slew Rate
I_SR
–
TBD
–
mA/µs
Fault Condition Timeout
t_FAULT
–
1.0
–
ms
Retry Timer Cycle
t_Ret
–
100
–
ms
SCA, SCL PIN, I²C BUS (STANDARD)
SCL Clock Frequency
f_SCL
0
–
100
kHz
Bus Free Time Between a STOP and a START Condition
t_BUF
4.7
–
–
µs
Hold Time (Repeated) START Condition (After this period, the first clock pulse
t_HD-STA
is generated.)
4.0
–
µs
–
Low Period of the SCL Clock
t_LOW
4.7
–
–
µs
High Period of the SCL Clock
t_HIGH
4.0
–
–
µs
SDA Fall Time from V_{IH_MAX} to V_{IL_MIN}, Bus Capacitance 10 pF to 400 pF,
t_F
3.0 mA Sink Current
ns
–
–
250
Setup Time for a Repeated START Condition
t_SU-STA
4.7
–
–
µs
Data Hold Time for I²C bus devices (Note 10), (Note 11)
t_HD-DAT
0
–
–
µs
Data Setup Time
t_SU-DAT
250
–
–
ns
Setup Time for STOP Condition
t_SU-STO
4.0
–
–
µs
Capacitive Load for Each Bus Line
C_B
–
–
400
pF
Notes
10. Design Information only. Not production tested.
11. The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the V_{IH_MIN} of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
Timing Diagram
t_HD-STA
t_HD-STA
t_HD-DAT
t_SU-DAT
t_SU-STA
Figure 2. Definition of Time on the I²C Bus
MOTOROLA ANALOG INTEGRATED CI_FRC_oU_rIT_MD_oE_rV_eICE_InD_fA_oT_rA_{mation On This Product,}
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t_SU-STO
33702
11