MC56F8346 Datasheet, PDF (107/160 Pages) Motorola, Inc – 56F8346 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
Register Descriptions
Table 6-2 Control of Pads Using SIM_GPS Control ¹
Control Registers
Pin Function
Comments
GPIO Input
0
0
—
—
GPIO Output
0
1
—
—
Quad Timer Input / 1
—
0
0
See the “Switch Matrix for Inputs to the Timer”
Quad Decoder
Input ²
table in the 56F8300 Peripheral User Manual
for the definition of the timer inputs based on
the Quad Decoder Mode configuration.
Quad Timer
1
—
0
1
Output / Quad
Decoder Input ³
SPI input
SPI output
1
—
1
—
1
— See SPI controls for determining the direction
of each of the SPI pins.
1
—
1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control
bits is used for each pin.
2. Reset configuration
3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.
Base + $B
Read
Write
RESET
15 14 13 12 11 10 9 8 7 6 5 4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
C3
C2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)
1
0
C1
C0
0
0
6.5.8.1 Reserved—Bits 15–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.8.2 GPIO C3 (C3)—Bit 3
This bit selects the alternate function for GPIOC3.
• 0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register
in the 56F8300 Peripheral User Manual)
• 1 = SS1
6.5.8.3 GPIO C2 (C2)—Bit 2
This bit selects the alternate function for GPIOC2.
• 0 = INDEX1/TB2 (default)
• 1 = MISO1
56F8346 Technical Data
107
Preliminary
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