MC56F8346 Datasheet, PDF (100/160 Pages) Motorola, Inc – 56F8346 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
Add. Register
Offset Name
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
$0
SIM_
R
CONTROL _W
0
0
0
0
0
0
0
0
0
0 _{ONCE SW}
EBL RST
STOP_
DISABLE
WAIT_
DISABLE
$1
SIM_
R0
RSTSTS _W
0
0
0
0
0
0
0
0
0
0
0
SWR COPR EXTR POR
R
$2 SIM_SCR0
W
FIELD
R
$3 SIM_SCR1
W
FIELD
R
$4 SIM_SCR2
W
FIELD
R
$5 SIM_SCR3
W
FIELD
$6
SIM_MSH_ ^R
ID
W
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
R0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
$7 SIM_LSH_ID _W
$8
R
SIM_PUDR
W
0
PWMA
1
CAN
EMI_
MODE
RESET
IRQ
XBOOT PWMB
PWMA
0
0
CTRL
0
JTAG
0
0
0
Reserved
$A
SIM_
R0
CLKOSR _W
0
0
0
0
0
A23 A22 A21 A20 CLKDIS
CLKOSEL
R0
0
0
0
0
0
0
0
0
0
0
0
$B SIM_GPS
C3 C2 C1 C0
W
$C
SIM_PCE
R
W
EMI
ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI1
SCI0 SPI1
SPI0
PWM PWM
B
A
R1
1
1
1
1
1
1
1
1
1
1
1
1
1
$D SIM_ISALH
ISAL[23:22]
W
R
$E SIM_ISALL
W
ISAL[21:6]
= Reserved
Figure 6-2 SIM Register Map Summary
6.5.1 SIM Control Register (SIM_CONTROL)
Base + $0
Read
Write
RESET
15 14 13 12 11 10 9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0 _{ONCE SW}
STOP_
EBL RST DISABLE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-3 SIM Control Register (SIM_CONTROL)
1
0
WAIT_
DISABLE
0
0
6.5.1.1 Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.1.2 OnCE Enable (OnCE EBL)—Bit 5
• 0 = OnCE clock to 56800E core enabled when core TAP is enabled
• 1 = OnCE clock to 56800E core is always enabled
6.5.1.3 Software Reset (SWRST)—Bit 4
This bit is always read as 0. Writing a 1 to this field will cause the part to reset.
100
56F8346 Technical Data
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Preliminary