MC56F8346 Datasheet, PDF (1/160 Pages) Motorola, Inc – 56F8346 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
MC56F8346/D
Rev. 8.0, 6/2004
56F8346
Preliminary Technical Data
56F8346 16-bit Hybrid Controller
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 1MB of off-chip program and data
memory
• Chip Select Logic for glueless interface to ROM
and SRAM
• 128KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 8KB of Data RAM
• 8KB of Boot Flash
• Two 6-channel PWM Modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
• Two Quadrature Decoders
• Optional On-Chip Regulator
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 62 GPIO lines
• 144-pin LQFP Package
OCR_DIS
EMI_MODE
RSTO
EXTBOOT
RESET
5
V_PP
2
V_CAP V_DD
4
7
V_SS
5
V_DDA
2
V_SSA
6 _{PWM Outputs}
PWMA
3
Current Sense Inputs
or GPIOC
3
Fault Inputs
JTAG/
EOnCE
Port
Digital Reg Analog Reg
16-Bit
Low Voltage
56800E Core ^Supervisor
6 _{PWM Outputs}
PWMB
Program Controller
and
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Bit
Manipulation
3
Current Sense Inputs
Hardware Looping Unit
Three 16-bit Input Registers
Unit
or GPIOD
Four 36-bit Accumulators
4
Fault Inputs
PAB
4
AD0
4
ADCA
AD1
PDB
CDBR
CDBW
5
VREF
Memory
4
AD0
XDB2
Program Memory XAB1
4
ADCB
AD1
64K x 16 Flash
2K x 16 RAM
XAB2
Temp_Sense
4K x 16 Boot
PAB
Quadrature
Flash
PDB
R/W Control
6
External
Address Bus
2
Switch
8
System Bus
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0 or A16
4
Decoder 0 or
CDBR
Quad
Data Memory
Timer A or
4K x 16 Flash
CDBW
GPIOC
4K x 16 RAM
Control
7
External Data
Bus Switch ₉
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
Quadrature
Decoder 1 or
4
Quad
Timer B or
IPBus Bridge (IPBB)
Bus Control ²
WR
RD
GPIOD0-1 or CS2-3
SPI1 or
GPIOC
Quad
Timer C or
Decoding
Peripheral
Device Selects
RW
IPAB
Control
IPWDB
IPRDB
PS (CS0) or GPIOD8
DS (CS1) or GPIOD9
GPIOE
Quad ^Peripherals
2
Timer D or
GPIOE
Clock
resets
PLL
2
FlexCAN
SPI0 or
GPIOE
SCI1 or
GPIOD
SCI0 or
COP/
Interrupt
GPIOE Watchdog Controller
System
P
O
Integration R
Module
Clock ^O
Generator
S
C
XTAL
EXTAL
4
2
2
IRQA IRQB
CLKO
CLKMODE
56F8346 Block Diagram - 144 LQFP
© Motorola, Inc., 2004. All rights reserved.
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