56F8345 Datasheet, PDF (105/148 Pages) Motorola, Inc – 56F8345 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
Register Descriptions
6.5.8.4 GPIO C1 (C1)—Bit 1
This bit selects the alternate function for GPIO C1.
• 0 = PHASEB1/TB1 (default)
• 1 = MOSI1
6.5.8.5 GPIO C0 (C0)—Bit 0
This bit selects the alternate function for GPIO C0.
• 0 = PHASEA1/TB0 (default)
• 1 = SCLK1
6.5.9 Peripheral Clock Enable Register (SIM_PCE)
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a
power savings feature. The clocks can be individually controlled for each peripheral on the chip.
Base + $C
Read
Write
RESET
15 14 13 12 11 10 9
8
7
6
54
3
EMI ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI1 SCI0 SPI1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
0
SPI0 PWMB PWMA
1
1
1
Figure 6-12 Peripheral Clock Enable Register (SIM_PCE)
6.5.9.1 External Memory Interface Enable (EMI)—Bit 15
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.2 Analog-to-Digital Converter B Enable (ADCB)—Bit 14
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.3 Analog-to-Digital Converter A Enable (ADCA)—Bit 13
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
6.5.9.4 FlexCAN Enable (CAN)—Bit 12
Each bit controls clocks to the indicated peripheral.
• 1 = Clocks are enabled
• 0 = The clock is not provided to the peripheral (the peripheral is disabled)
56F8345 Technical Data
105
Preliminary
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