56F8345 Datasheet, PDF (1/148 Pages) Motorola, Inc – 56F8345 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
MC56F8345/D
Rev. 8.0, 6/2004
Preliminary Technical Data
56F8345 16-bit Hybrid Controller
56F8345
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 128KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• Two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
• Two Quadrature Decoders
• FlexCAN module
• Optional On-Chip Regulator
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interface (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 49 GPIO lines
• 128-pin LQFP Package
6 _{PWM Outputs}
3
Current Sense Inputs
or GPIOC
4
Fault Inputs
PWMA
6 _{PWM Outputs}
3
Current Sense Inputs
or GPIOD
4
Fault Inputs
PWMB
4
AD0
4
ADCA
AD1
Memory
5
VREF
Program Memory
4
AD0
64K x 16 Flash
ADCB
2K x 16 RAM
4
AD1
4K x 16 Boot
Flash
TEMP_SENSE
Quadrature ^{Data Memory}
4
Decoder 0 or
Quad
4K x 16 Flash
4K x 16 RAM
Timer A or
GPIOC
Quadrature
4
Decoder 1 or
Quad
Timer B or
SP1I or
GPIOC _Decoding
2 ^{Quad Timer Peripherals}
C or GPIOE
4
Quad Timer
D or GPIOE
2
FlexCAN
SPI0 or
GPIOE
RSTO
RESET
5
V_PP
2
OCR_DIS
V_CAP V_DD V_SS V_DDA
4
7
52
V_SSA
JTAG/
EOnCE
Port
Digital Reg Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Program Controller
Address
and Hardware Generation Unit
Looping Unit
Data ALU
16 x 16 + 36 -->36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
* External ⁶
Address Bus
Switch
5
* External
Data
4
Bus Switch
A8-13 or GPIOA0-5
GPIOB0-4 or A16-20
D7-10 or GPIOF0-3
IPBus Bridge (IPBB)
* Bus
6
Control
GPIOD0-5 or CS2-7
Peripheral
Device Selects
RW IPAB IPWDB
Control
IPRDB
Clock
resets
PLL
* EMI not functional in
this package; use as
GPIO pins
SCI1 or SCI0 or COP/ Interrupt
GPIOD GPIOE Watchdog Controller
System
P
O
Integration R
Module
Clock O
Generator
S
C
XTAL
EXTAL
4
2
2
IRQA IRQB
CLKO
CLKMODE
56F8345 Block Diagram - 128 LQFP
© Motorola, Inc., 2004. All rights reserved.
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