56F8345 Datasheet, PDF (10/148 Pages) Motorola, Inc – 56F8345 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
Table 1-1 Bus Signal Names
Name
Function
Program Memory Interface
pdb_m[15:0] Program data bus for instruction word fetches or read operations.
cdbw[15:0]
Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)
pab[20:0]
Program memory address bus. Data is returned on pdb_m bus.
Primary Data Memory Interface Bus
cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.
cdbw[31:0] Primary core data bus for memory writes. Addressed via xab1 bus.
xab1[23:0]
Primary data address bus. Capable of addressing bytes¹, words, and long data types. Data is written
on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
Secondary Data Memory Interface
xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
xab2[23:0]
Secondary data address bus used for the second of two simultaneous accesses. Capable of
addressing only words. Data is returned on xdb2_m.
Peripheral Interface Bus
IPBus [15:0]
Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0.
1.5 Product Documentation
The documents listed in Table 1-2 are required for a complete description and proper design with
the 56F8345. Documentation is available from local Motorola distributors, Motorola
semiconductor sales offices, Motorola Literature Distribution Centers, or online at
http://www.motorola.com/semiconductors.
Topic
DSP56800E
Reference Manual
56F8300 Peripherals
Manual
56F8300 SCI/CAN
Bootloader User Manual
56F8345
Technical Data Sheet
56F8345
Product Brief
56F8345
Errata
Table 1-2 56F8345 Chip Documentation
Description
Detailed description of the 56800E family architecture,
16-bit hybrid controller core processor, and the
instruction set
Detailed description of peripherals of the 56F8300
family of devices
Detailed description of the SCI/CAN Bootloaders
56F8300 family of devices
Electrical and timing specifications, pin descriptions,
device specific peripheral information and package
descriptions (this document)
Summary description and block diagram of the
56F8345 core, memory, peripherals and interfaces
Details any chip issues that might be present
Order Number
DSP56800ERM/D
MC56F8300UM/D
MC56F83xxBLUM/D
MC56F8345/D
MC56F8345PB/D
MC56F8345E/D
10
56F8345 Technical Data
For More Information On This Product,
Go to: www.freescale.com
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