MMDF2C02HD Datasheet, PDF (1/12 Pages) Motorola, Inc – COMPLEMENTARY DUAL TMOS POWER FET 2.0 AMPERES 20 VOLTS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMDF2C02HD/D
™ Designer's Data Sheet
Medium Power Surface Mount Products
Complementary TMOS
Field Effect Transistors
MiniMOS™ devices are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain–to–source diode has a very low reverse recovery time.
™
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc–dc converters, and power management in
D
portable and battery powered products such as computers, ^{N–Channel}
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to
eliminate the guesswork in designs where inductive loads are ^G
switched and offer additional safety margin against unexpected
voltage transients.
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• Ultra Low RDS(on) Provides Higher Efficiency and Extends
Battery Life
• Logic Level Gate Drive — Can Be Driven by Logic ICs
D
P–Channel
• Miniature SO–8 Surface Mount Package — Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
G
• Avalanche Energy Specified
• Mounting Information for SO–8 Package Provided
S
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)(1)
Rating
MMDF2C02HD
Motorola Preferred Device
COMPLEMENTARY
DUAL TMOS POWER FET
2.0 AMPERES
20 VOLTS
RDS(on) = 0.090 OHM
(N–CHANNEL)
RDS(on) = 0.160 OHM
(P–CHANNEL)
CASE 751–05, Style 14
SO–8
N–Source
N–Gate
P–Source
P–Gate
18
27
36
45
Top View
N–Drain
N–Drain
P–Drain
P–Drain
Symbol
Value
Unit
Drain–to–Source Voltage
Gate–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 mΩ)
Drain Current — Continuous
— Pulsed
N–Channel
P–Channel
N–Channel
P–Channel
Operating and Storage Temperature Range
Total Power Dissipation @ TA= 25°C ⁽²⁾
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 20 V, VGS = 5.0 V, Peak IL = 9.0 A, L = 10 mH, RG = 25 Ω)
(VDD = 20 V, VGS = 5.0 V, Peak IL = 6.0 A, L = 18 mH, RG = 25 Ω)
Thermal Resistance — Junction to Ambient ⁽²⁾
N–Channel
P–Channel
Maximum Lead Temperature for Soldering, 0.0625″ from case. Time in Solder Bath is 10 seconds.
DEVICE MARKING
VDSS
VGS
VDGR
ID
IDM
TJ, Tstg
PD
EAS
R_θJA
TL
20
± 20
20
3.8
3.3
19
20
– 55 to 150
2.0
405
324
62.5
260
Vdc
Vdc
Vdc
A
°C
Watts
mJ
°C/W
°C
D2C02
(1) Negative signs for P–Channel device omitted for clarity.
(2) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with one die operating, 10 sec. max.
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MMDF2C02HDR2
13″
12 mm embossed tape
2500 units
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 5
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