M32C Datasheet, PDF (85/441 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Interrupts
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of the built-in peripheral functions. Built-in peripheral
functions are dependent on classes of products, so the interrupt factors too are dependent on classes
of products. The interrupt vector table is the same as the one for software interrupt numbers 7 through
54 and 57 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• UART related interrupt (UART0 to 4)
- UART transmission/NACK interrupt
- UART reception/ACK interrupt
- Bus collision detection, start/stop condition detection interrupts
This is an interrupt that the serial I/O bus collision detection generates. When I²C mode is selected,
start, stop condition interrupt is selected.
• DMA0 through DMA3 interrupts
• Key-input interrupt
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A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt (AD0, 1)
• Timer A interrupt (TA0 to 4)
• Timer B interrupt (TB0 to 5)
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_______
________
• INT interrupt (INT0 to INT5 )
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_____
An INT interrupt selects an edge sense or a level sense. In edge sense, an INT interrupt occurs if
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_____
either a rising edge or a falling edge is input to the INT pin. In level sense, an INT interrupt occurs if
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either a "H" level or a "L" level is input to the INT pin.
• Intelligent I/O interrupt
• CAN interrupt
High-speed interrupts
High-speed interrupts are interrupts in which the response is executed at 5 cycles and the return is 3
cycles.
When a high-speed interrupt is received, the flag register (FLG) and program counter (PC) are saved to
the save flag register (SVF) and save PC register (SVP) and the program is executed from the address
shown in the vector register (VCT).
Execute an FREIT instruction to return from the high-speed interrupt routine.
High-speed interrupts can be set by setting “1” in the high-speed interrupt specification bit allocated to bit
3 of the exit priority register. Setting “1” in the high-speed interrupt specification bit makes the interrupt set
to level 7 in the interrupt control register a high-speed interrupt.
You can only set one interrupt as a high-speed interrupt. When using a high-speed interrupt, do not set
multiple interrupts as level 7 interrupts. When using high speed interrupt, DMA II cannot be used.
The interrupt vector for a high-speed interrupt must be set in the vector register (VCT).
When using a high-speed interrupt, you can use a maximum of two DMAC channels.
The execution speed is improved when register bank 1 is used with high speed interrupt register selected
by not saving registers to the stack but to the switching register bank. In this case, switch register bank
mode for high-speed interrupt routine.
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