M32C Datasheet, PDF (178/441 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Udnedveerlopment ^{Rev.B2 for proof reading}
Clock synchronous serial I/O mode
Mitsubishi Microcomputers
M32C/83 group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.18.2. Specifications of clock synchronous serial I/O mode (2/2)
Item
Error detection
• Overrun error ^(Note)
Specification
This error occurs when the next data is started to receive and 6.5 transfer clock is
elapsed before UARTi receive buffer register are read out.
Select function
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the transfer
clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Reversing serial data logic
Whether to reverse data in writing to the transmission buffer register or reading the
reception buffer register can be selected.
• TxD, RxD I/O polarity reverse
This function is reversing TxD port output and RxD port input. All I/O data level is
reversed.
Note : If an overrun error occurs, the UARTi receive buffer will have the next data written in.
Table 1.18.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note
that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin
outputs a “H”. (If the N-channel open drain is selected, this pin is in floating state.)
Table 1.18.3. Input/output pin functions in clock synchronous serial I/O mode
Pin name
Function
Method of selection
TxDi
Serial data output
(P63, P67, P70, _{(Note 1)}
P92, P96)
(Outputs dummy data when performing reception only)
RxDi
Serial data input
(P62, P66, P71, (Note 2)
P91, P97)
Port P62, P66, P71, P91 and P97 direction register (bits 2 and 6 at address
03C216, bit 1 at address 03C316, bit 1 and 7 at address 03C716)= “0”
(Can be used as an input port when performing transmission only)
CLKi
Transfer clock output
(P61, P65, P72, (Note 1)
P90, P95)
Transfer clock input
(Note 2)
Internal/external clock select bit (bit 3 at addresses 036816, 02E816,
033816, 032816, 02F816) = “0”
Internal/external clock select bit (bit 3 at addresses 036816, 02E816,
033816, 032816, 02F816) = “1”
Port P61, P65, P72, P90 and P95 direction register (bits 1 and 5 at address
03C216, bit 2 at address 03C316, bit 0 and 5 at address 03C716) = “0”
CTSi/RTSi
CTS input
(P60, P64, P73, (Note 2)
P93, P94)
RTS output (Note 1)
CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16, 032C16,
02FC16) =“0”
CTS/RTS function select bit (bit 2 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “0”
Port P60, P64, P73, P93 and P94 direction register (bits 0 and 4 at address
03C216, bit 3 at address 03C316, bits 3 and 4 at address 03C716) = “0”
CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “0”
CTS/RTS function select bit (bit 2 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “1”
Programmable I/O port
(Note 2)
CTS/RTS disable bit (bit 4 at addresses 036C16, 02EC16, 033C16,
032C16, 02FC16) = “1”
________
Note 1: Select TxD output, CLK output and RTS output by the corresponding function select registers A, B and C.
Note 2: Select I/O port by the corresponding function select register A.
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