PSS30S71F6 Datasheet, PDF (8/12 Pages) Mitsubishi Electric Semiconductor – Dual-In-Line Package Intelligent Power Module

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PSS30S71F6
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 6 Example of Application Circuit
+
C1 D1 C2
C2
VUFB(3)
VUFS(1)
VP1(4)
UP(6)
+
C1 D1 C2
C2
VVFB(9)
VVFS(7)
VP1(10)
VP(12)
+
C1 D1 C2
C2
VWFB(15)
VWFS(13)
VP1(16)
WP(18)
5kΩ
5V
R2
VOT(20)
UN(21)
VN(22)
WN(23)
Fo(24)
CFO(25)
HVIC
HVIC
HVIC
LVIC
IGBT1
Di1
IGBT2
Di2
IGBT3
Di3
IGBT4
Di4
IGBT5
Di5
IGBT6
Di6
P
U
V_M
W
+
C3
NU
NV
15V
VD
C1 ⁺ D1
C2
Long GND wiring here might
generate noise to input signal and
cause IGBT malfunction.
VN1(28)
VNC(27)
CIN(26)
B
C4
NW
Long wiring here might cause SC
level fluctuation and malfunction.
Long wiring here might
cause short circuit failure
C
R1
A
D
Shunt resistor
Control GND wiring ^N1 Power GND wiring
(1) If control GND is connected with power GND by common broad pattern, it may cause malfunction by power GND fluctuation.
It is recommended to connect control GND and power GND at only a point N1 (near the terminal of shunt resistor).
(2) It is recommended to insert a Zener diode D1(24V/1W) between each pair of control supply terminals to prevent surge destruction.
(3) To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible.
Generally a 0.1-0.22μF snubber capacitor C3 between the P-N1 terminals is recommended.
(4) R1, C4 of RC filter for preventing protection circuit malfunction is recommended to select tight tolerance, temp-compensated type.
The time constant R1C4 should be set so that SC current is shut down within 2μs. (1.5μs~2μs is recommended generally.) SC
interrupting time might vary with the wiring pattern, so the enough evaluation on the real system is necessary.
(5) To prevent malfunction, the wiring of A, B, C should be as short as possible.
(6) The point D at which the wiring to CIN filter is divided should be near the terminal of shunt resistor. NU, NV, NW terminals should be
connected at near NU, NV, NW terminals when it is used by one shunt operation. Low inductance SMD type with tight tolerance,
temp-compensated type is recommended for shunt resistor.
(7) All capacitors should be mounted as close to the terminals as possible. (C1: good temperature, frequency characteristic electrolytic
type and C2:0.22μ-2μF, good temperature, frequency and DC bias characteristic ceramic type are recommended.)
(8) Input logic is High-active. There is a 3.3kΩ(min.) pull-down resistor in the input circuit of IC. To prevent malfunction, the input wiring
should be as short as possible. When using RC coupling, make the input signal level meet the turn-on and turn-off threshold voltage.
(9) Fo output is open drain type. It should be pulled up to power supply of MCU (e.g. 5V,3.3V) by a resistor that makes IFo up to 1mA.
(IFO is estimated roughly by the formula of control power supply voltage divided by pull-up resistance. In the case of pulled up to 5V,
10kΩ (5kΩ or more) is recommended.) When using opto coupler, Fo also can be pulled up to 15V (control supply of DIPIPM) by the
resistor.
(10) Fo pulse width can be set by the capacitor connected to CFO terminal. CFO(F) = 9.1 x 10^-6 x tFO (Required Fo pulse width).
(11) If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous
operation. To avoid such problem, line ripple voltage should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p.
(12) For DIPIPM, it isn't recommended to drive same load by parallel connection with other phase IGBT or other DIPIPM.
Publication Date : December 2013
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