M38B5XMXH Datasheet, PDF (44/355 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

HARDWARE
FUNCTIONAL DESCRIPTION
Serial I/O
qSerial I/O1
Serial I/O1 is used as the clock synchronous serial I/O and has an
ordinary mode and an automatic transfer mode. In the automatic
transfer mode, serial transfer is performed through the serial I/O
automatic transfer RAM which has up to 256 bytes (addresses
0F0016 to 0FFF16: addresses 0F6016 to 0FFF16 are also used as
FLD automatic display RAM).
The P62/SRDY1/AN8, P64/INT4/SBUSY1/AN10, and P65/SSTB1/AN11
pins each have a handshake I/O signal function and can select
either “H” active or “L” active for active logic.
Main address Local address
bus
bus
Serial I/O automatic
transfer RAM
(0F0016—0FFF16)
Main Local
data bus data bus
Address decoder
Serial I/O1
automatic transfer
data pointer
Serial I/O1
automatic transfer
controller
XCIN
XIN
1/2
Internal system
clock selection bit
“1”
“0”
P65 latch
Serial I/O1
control register 3
1/4
1/8
1/16
1/32
“0” _{(P65/SSTB1 pin control bit)}
1/64
P65/SSTB1
P62/SRDY1•P64/SBUSY1
pin control bit
“1”
P64 latch
“0”
P64/SBUSY1
“1”
P62/SRDY1•P64/SBUSY1
pin control bit
P62 latch
“0”
P62/SRDY1
“1”
1/128
1/256
Serial I/O1
synchronous clock
selection bit _{“0”}
Internal synchronous
clock selection bits
Synchronous
circuit
“1”
Serial I/O1 clock
pin selection bit
P52 latch
“0”
“1”
Serial transfer
status flag
P52/SCLK11
P53/SCLK12
“0”
“0”
“1”
“1”
“1”
Serial I/O1 clock
“0”
pin selection bits
Serial I/O1 counter
P51/SOUT1
P53 latch
“0” _{P51 latch}
“1” Serial transfer selection bits
P50/SIN1
Serial I/O1 register (8)
Serial I/O1
interrupt request
Fig. 21 Block diagram of serial I/O1
1-28
38B5 Group User’s Manual