M38B5XMXH Datasheet, PDF (156/355 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.3 Serial I/O
The communication is performed according to the timing shown in Figure 2.3.45. In the slave unit,
when a synchronous clock is not input within a certain time (heading adjusment time), the next clock
input is processed as the beginning (heading) of a block.
When a clock is input again after one block (8 bytes) is received, the clock is ignored.
Figure 2.3.46 shows the relevant registers setting in the master unit and Figure 2.3.47 shows the
relevant registers setting in the slave unit.
D0
D1
D2
D7
D0
Byte cycle
Block transfer term
Interval between blocks
Block transfer cycle
Heading adjustment time
Fig. 2.3.45 Timing chart
Processing for heading adjustment
Master unit
Serial I/O2 control register (address 001D16)
SIO2CON _{1 1 1 1 1 0 0 0}
BRG count source : f(XIN)
Synchronous clock : BRG/4
SRDY2 output disabled
Transmit interrupt source : Transmit shift operating completion
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 001716)
UARTCON 0 0 0
P55/TxD pin: CMOS output
BRG clock: f(XIN)
Serial I/O2 clock: SCLK21
Baud rate generator (address 001616)
BRG
0716
Set “division ratio – 1”
Fig. 2.3.46 Relevant registers setting in master unit
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38B5 Group User’s Manual