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M38B5XMXH Datasheet, PDF (20/355 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER | |||
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HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
VCC, VSS
VEE
VREF
AVSS
______
RESET
XIN
Power source
Pull-down
power source
Reference
voltage
Analog power
source
Reset input
Clock input
XOUT
Clock output
P00/FLD8â I/O port P0
P07/FLD15
P10/FLD16â Output port P1
P17/FLD23
P20/BUZ02/ I/O port P2
FLD0â
P27/FLD7
P30/FLD24â Output port P3
P37/FLD31
P40/INT0,
P41/INT1,
P42/INT3
P43/BUZ01
P44/PWM1
I/O port P4
P45/T1OUT,
P46/T3OUT
P47/INT2
Input port P4
Function
⢠Apply voltage of 4.0â5.5 V to VCC, and 0 V to VSS.
⢠Apply voltage supplied to pull-down resistors of ports P0, P1, and P3.
Function except a port function
⢠Reference voltage input pin for A-D converter.
⢠Analog power source input pin for A-D converter.
⢠Connect to VSS.
⢠Reset input pin for active âL.â
⢠Input and output pins for the main clock generating circuit.
⢠Feedback resistor is built in between XIN pin and XOUT pin.
⢠Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
⢠When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
⢠The clock is used as the oscillating source of system clock.
⢠8-bit I/O port.
⢠FLD automatic display
⢠I/O direction register allows each pin to be individually programmed as either pins
input or output.
⢠At reset, this port is set to input mode.
⢠A pull-down resistor is built in between port P0 and the VEE pin.
⢠CMOS compatible input level.
⢠High-breakdown-voltage P-channel open-drain output structure.
⢠At reset, this port is set to VEE level.
⢠8-bit output port.
⢠FLD automatic display
⢠A pull-down resistor is built in between port P1 and the VEE pin.
pins
⢠High-breakdown-voltage P-channel open-drain output structure.
⢠At reset, this port is set to VEE level.
⢠8-bit I/O port with the same function as port P0.
⢠FLD automatic display
⢠Low-voltage input level.
pins
⢠High-breakdown-voltage P-channel open-drain output structure.
⢠Buzzer output pin (P20)
⢠8-bit output port.
⢠FLD automatic display
⢠A pull-down resistor is built in between port P3 and the VEE pin.
pins
⢠High-breakdown-voltage P-channel open-drain output structure.
⢠At reset, this port is set to VEE level.
⢠7-bit I/O port with the same function as port P0.
⢠Interrupt input pins
⢠CMOS compatible input level
In the mask option type P,
⢠N-channel open-drain output structure.
INT3 cannot be used.
⢠Buzzer output pin
⢠PWM output pin
(Timer output pin)
⢠Timer output pin
⢠1-bit input port.
⢠CMOS compatible input level.
⢠Interrupt input pin
1-4
38B5 Group Userâs Manual
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