M38B5XMXH Datasheet, PDF (246/355 Pages) Mitsubishi Electric Semiconductor – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.11 Clock generating circuit
Control procedure: Set the relevant registers in the order shown below to prepare for a power
failure.
RESET
qX: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
CPUM (address 003B16), bit 4
CPUM (address 003B16), bit 6
T1 (address 002016)
T12M (address 002816)
T34M (address 002916)
IREQ1 (address 003C16), bit 7, bit 5
Base counter (internal RAM)
1 second counter (internal RAM)
ICON1 (address 003E16), bit 5
1
0
3F16
000010002
00XX01X02
0,0
FF16
0F16
1
Port XC: XCIN-XCOUT oscillation function
When selecting main clock f(XIN) (high-speed mode)
Setting for making base and one second counters activate during
timer 1 interrupt
In the normal power state, these software counters generate one
second.
N
Detect power failure ?
Y
≈
T12M (address 002816), bit 3, bit 2
ICON1 (address 003E16), bit 5
CPUM (address 003B16), bit 7
CPUM (address 003B16), bit 5
IREQ1 (address 003C16), bit 7, bit 5
T1 (address 002016)
T2 (address 002116)
T3 (address 002216)
0, 1
0
1 (Note)
1 (Note)
0, 0
0716
3F16
0F16
Timer 1 count source: f(XCIN)
Timer 1 interrupt: Disabled
Internal system clock: f(XCIN) (low-speed mode)
Main clock f(XIN): Oscillation stopped
Setting for generating timer 3 interrupt every second
Generation of one second by hardware timer during
power failure
ICON1 (address 003E16), bit 7
1
Execute WIT instruction
N
Return condition for power failure is
satisfied ?
Y
Return processing from power failure
≈
Fig. 2.11.9 Control procedure
Timer 3 interrupt: Enabled
Timer 3 interrupt occurs every second
(return from wait mode)
Note: Do not switch at one time.
2-158
38B5 Group User’s Manual