M38258MCM Datasheet, PDF (36/70 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI MICROCOMPUTERS
3825 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK OUTPUT FUNCTION
Input/output ports P40 and P41 can output clock. The input/output
ports and clock output function are put under double function con-
trolled by the clock output control register (address 002A16).
Selection of Input/Output Ports and Clock
Output Function
Bits 0 and 1 of the clock output control register can select between
the input/output ports and the clock output function.
When selecting the clock output function, clocks are output while
the direction register of ports P40 and P41 are set to output.
At the next cycle of rewriting the clock output control bit, P40 is
switched between the port output and the clock output.
In synchronization with the fall of the clock (resulting from dividing
XIN by 5) on rewriting the clock output control bit, P41 is switched
between the port output and the clock output.
Selection of Output Clock Frequency
Bit 2 (output clock frequency selection bit) of the clock output con-
trol register selects an output clock frequency.
When setting the output clock frequency selection bit to “0”, port
P40 becomes the frequency of f(XIN) and port P41 becomes the
frequency of f(XIN)/5.
At this time, the output pulse of port P40 depends on the XIN input
pulse, while the output pulse of port P41 has duty ratio of about
40%.
When setting the output clock frequency selection bit to “1”, port
P40 becomes the frequency of f(XIN)/2 and port P41 becomes the
frequency of f(XIN)/10. At this time, the output pulses of both ports
P40 and P41 have duty ratio of 50%.
b7
b0
Clock output control register
(TCON : address 002A16)
P40 clock output control bit
0 : I/O port
1 : Clock output
P41 clock output control bit
0 : I/O port
1 : Clock output
Output clock frequency selection bit
0 : P40←f(XIN), P41←f(XIN)/5
1 : P40←f(XIN)/2, P41←f(XIN)/10
Not used (return “0” when read)
Fig. 34 Structure of clock output control register
P40 port latch
P40 clock output
“0” _{control bit}
“0”
XIN
P40
“1” _{Output clock}
“1”
1/2
frequency
selection bit
P40 direction register
P41 port latch
P41 clock output
“0” _{control bit}
“0”
1/5
P41
“1” _{Output clock}
“1”
1/2
frequency
selection bit
P41 direction register
Fig. 35 Clock output function block diagram
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