M2S56D20TP Datasheet, PDF (32/36 Pages) Mitsubishi Electric Semiconductor – 256M Double Data Rate Synchronous DRAM

DDR SDRAM (Rev.0.0)
Sep.'99 Preliminary
[Initialize and Mode Register sets]
/CLK
CLK
MITSUBISHI LSIs
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
Command
A0-9,11,12
A10
BA0,1
DQS
DQ
NOP
PRE
EMRS
MRS
PRE
AR
Code
Code
1
Code
Code
1
10
00
AR
MRS
ACT
Xa
Code
Xa
00
Xa
tMRD tMRD tRP tRFC tRFC tMRD
[AUTO REFRESH]
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command.
The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbits memory
cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto refresh, all
banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC . Any command
must not be supplied to the device before tRFC from the REFA command.
/CLK
CLK
Auto-Refresh
/CS
/RAS
NOP or DESELECT
/CAS
/WE
CKE
A0-12
BA0,1
tRFC
Auto Refresh on All Banks
Auto Refresh on All Banks
MITSUBISHI
ELECTRIC
32