M2S56D20TP Datasheet, PDF (1/36 Pages) Mitsubishi Electric Semiconductor – 256M Double Data Rate Synchronous DRAM

DDR SDRAM (Rev.0.0)
Sep.'99 Preliminary
MITSUBISHI LSIs
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
M2S56D20TP is a 4-bank x 16777216-word x 4-bit,
M2S56D30TP is a 4-bank x 8388608-word x 8-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output
data and data strobe are referenced on both edges of CLK. The M2S56D20/30 TP achieves very high
speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5v±0.2V
- Double data rate architecture;
two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
with CLK transitions edges of DQS
- Commands entered on each positive CLK edge;
- data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 1.5/2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)
- SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- FET switch control(/QFC)
- JEDEC standard
PIN CONFIGURATION
(TOP VIEW)
x8
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU/QFC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
66
2
65
3
64
4
63
5
62
6
7
66pin TSOP(II)
61
60
8
59
9
58
10
57
11
56
12
13
400mil width
55
54
14
x
53
15 _{875mil length} 52
16
51
17
50
18
49
19
20
21
0.65mm
Lead Pitch
48
47
46
22
45
23
44
24
25
ROW
43
42
26 A0-12
41
27
28
29
Column
A0-9,11(x4)
40
39
38
30
A0-9 (x8) 37
31
36
32
35
33
34
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
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