M2S56D20TP Datasheet, PDF (25/36 Pages) Mitsubishi Electric Semiconductor – 256M Double Data Rate Synchronous DRAM

DDR SDRAM (Rev.0.0)
Sep.'99 Preliminary
MITSUBISHI LSIs
M2S56D20/ 30 TP
256M Double Data Rate Synchronous DRAM
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from the
WRITE command with data strobe input, following (BL-1) data are written into RAM, when the Burst
Length is BL. The start address is specified by A11,A9-A0(x4)/A9-A0(x8), and the address sequence of
burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the
row precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks.
From the last data to the PRE command, the write recovery time (tWRP) is required. When A10 is high at
a WRITE command, the auto-precharge(WRITEA) is performed. Any
command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal precharge is complete.
The next ACT command can be issued after tDAL from the last input data cycle.
/CLK
CLK
Command
A0-9,11-12
A10
BA0,1
DQS
DQ
/CLK
CLK
Command
A0-9,11-12
A10
BA0,1
DQS
DQ
Multi Bank Interleaving WRITE (BL=8)
ACT
WRITE ACT
tRCD
Xa
Ya Xb
tRCD
WRITE
Yb
Xa
0 Xb
0
00
00 10
10
PRE
0
00
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Db2 Db3 Db4 Db5 Db6 Db7
WRITE with Auto-Precharge (BL=8)
ACT
WRITE
tRCD
Xa
Y
Xa
1
00
00
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
tDAL
ACT
Xb
Xb
00
PRE
0
10
MITSUBISHI
ELECTRIC
25