MT90812 Datasheet, PDF (78/105 Pages) Mitel Networks Corporation – Integrated Digital Switch (IDX)

MT90812
Advance Information
22.33 HRA Status 2 (HS2)
The register is configured as follows:
Read Address is: 56_H
Reset Value is: 80_H
7
6
5
TXCHNL TXACT CTSACT
4
FLAG
3
PRX4
2
PRX3
1
PRX2
0
PRX1
Bit
Name
Description
7
TXCHNL
TX Channel Number Latched (TXCHNL). The next TX channel number in write
register 3 has been latched by the TX control circuitry and may be rewritten when
this bit is high. The bit is automatically reset when a write to register 3 occurs. On
reset, this bit will be high, although the transmitter will be inactive.
6
TXACT
Transmitter Active (TXACT). When high, this status bit indicates that the
transmitter is currently active. On reset, this bit will be low, and TxCEN will be
disabled.
5
CTSACT
Clear-to-Send Active (CTSACT). See description in HS1 register.
4
FLAG
Flag Detect (FLAG). See description in HS1 register.
3-0
PRX4-1
Present Receive Channel (PRX). See description in HS1 register.
22.34 HRA Status 3 (HS3)
The register is configured as follows:
Read Address is: 57_H
Reset Value is: 80_H
7
6
5
TXCHNL RXCHNL
4
FLAG
3
PRX4
2
PRX3
1
PRX2
0
PRX1
Bit
Name
Description
7
TXCHNL
TX Channel Number Latched (TXCHNL).
6
RXCHNL
Receive Channel Latched (RXCHNL). See description in HS1 register.
5
unused
Unused.
4
FLAG
Flag Detect (FLAG). See description in HS1 register.
3-0
PRX4-1
Present Receive Channel (PRX). See description in HS1 register.
Reading the channel number via this register clears the status bit RXCHNL.
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