MT90812 Datasheet, PDF (19/105 Pages) Mitel Networks Corporation – Integrated Digital Switch (IDX)

Advance Information
MT90812
Channels can be transferred from Data Memory in either Minimum or Constant Delay to the Energy Detect and
DBRT blocks as specified in CMH. CMH Message Mode and Output Enable bits are ignored for locations 70-72
of CM.
In addition, CMH is used to specify the gain for the outgoing streams and the gain for the tones.
5.4 Use of Data Memory Reserved for Expansion Bus Streams
The use of the four blocks reserved for the expansion bus is dependent on the expansion bus mode set for the
device. The two expansion bus modes, TDM Link and IDX Link, are described on page 8. In TDM Link mode,
the four blocks are used according to the data rate set for the expansion bus. At 2.048 Mb/s the first 32 bytes,
00-1F, are used to store the incoming data. At 4.096 Mb/s the first 64 bytes, 00-3F are used. At 8.192 Mb/s all
128 locations, 00-7F, are used.
In IDX Link mode, 128 channels are read, 32 from EST1 and 96 from EST0. The positions that the MT90812
will read and write to the expansion bus are controlled by the EP1 and EP0 bits in Control Register B.
For example, a group of four MT90812 devices are labelled A, B, C, and D. The 128 channels on the expansion
bus streams are identified as A1, B1, C1, D1, A2, B2, C2, D2,...., A128, B128, C128, D128. The MT90812 with
EP1,EP0 set to 0,0 will read and write to EST0 and EST1 as listed in Table 5.
EST0
EST1
Expansion Bus Channel (i=1,32)
Ai
Bi
Ci
Write
Read
Read
Read
Write
Write
Table 5 - Expansion Bus Read/Write timeslots for IDX A
Di
Read
Write
The MT90812 with EP1,EP0 set to 0,0 will output on EST0 during channel Ai and will read the next three
channels Bi, Ci and Di. Channels Bi, Ci and Di go into Data Memory at Expansion Block 2, 3 and 4 respectively,
as shown in Table 2. Expansion block 1 will contain incoming channels on EST1 sent to IDX A in timeslots
labelled EA1,...,EA32 as shown in Figure 7 on page 9.
The MT90812 with EP1,EP0 set to 0,1 will output on EST0 and read EST1 during channel Bi and will read
EST0 and output on EST1 for channels Ai, Ci and Di.
The memory map for the expansion bus timeslots are shown in the Figures 8 - 12 for each of the four settings
of EP1 and EP0.
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