MT90812 Datasheet, PDF (36/105 Pages) Mitel Networks Corporation – Integrated Digital Switch (IDX)

MT90812
Advance Information
will specify whether the received data will have a parity bit and consequently the receiver will perform a parity
check on the received data.
In FLI Mode, the start and stop bits and the parity bit can be enabled or disabled with the SE and PE bits in the
DRXC Control register, respectively. With the start and stop bits enabled, the start of the message is identified
by the first ‘0’ received after the DBR is enabled. When the start and stop bits are disabled, no parity check will
be performed (regardless of the status of PE bit) and the data will be transferred from the incoming TDM
stream to the RX FIFO following the RX being enabled.
DSTI
Serial to Parallel
Data Memory
Channel m
Uport Read
Control Registers
DRXOUT = 43_HEX
DCHin CM 70H
Channel m
RX
RX FIFO
DBRX
Figure 22 - Data Flow for D-channel Receiver
11.1.1 Receiver Interrupt Handling
There are four interrupts associated with the D-channel Receiver. They are listed in Table 11.
Interrupts
DRX
DRE
OE
PE
SE
Register
INTS
INTS
DRXS
DRXS
DRXS
Reference Page
Description
page 56
D-Channel Receive Message Length or FIFO Level
interrupt
page 56
D-Channel Receive FIFO Error. Status of error in DCHS
register.
page 68
Receive Overrun Error
page 68
Receive Parity Error
page 68
Receive Stop Bit Error
Table 11 - D-Channel Receive Interrupts
The DREE and DRXE bits in the “Interrupt Enable Register (INTE)” on page 57 enable/disable the above
interrupts.
The main difference in MLI and FLI modes is in determining when the interrupt occurs. In MLI mode the
interrupt occurs when the full message has been received. In FLI mode the interrupt occurs when the number
of bytes in the FIFO equals the trigger level. The “D-Channel Receive Interrupt Threshold (DRXIT)” register is
used to program when an interrupt occurs for either MLI or FLI Mode. In the latter mode, the interrupt is to
indicate that the FIFO level is attained and not necessarily the end of the message. In the former mode, the
interrupt solely indicates the end of the message.
As listed in Table 11 an interrupt is also triggered when one of the following error conditions occurs:
• The RX FIFO is full and the next byte of data has been received and is to be transferred to the FIFO
then the overrun status bit is set and an interrupt occurs (RX overrun error).
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