MT9076 Datasheet, PDF (71/160 Pages) Mitel Networks Corporation – T1/E1/J1 3.3V Single Chip Transceiver

Preliminary Information
MT9076
Bit
Name
Functional Description
7 HDLC0IM HDLC0 Interrupt Mask. When unmasked an interrupt is triggered by an unmasked event in
HDLC0. If 1 - unmasked, 0 - masked.
6 HDLC1IM HDLC1 Interrupt Mask. When unmasked an interrupt is triggered by an unmasked event in
HDLC1. If 1 - unmasked, 0 - masked.
5 HDLC2IM HDLC2 Interrupt Mask. When unmasked an interrupt is triggered by an unmasked event in
HDLC2. If 1 - unmasked, 0 - masked.
4
LCDIM Loop Code Detected Interrupt Mask. When unmasked an interrupt is triggered when
either the loop up (00001) or loop down (001) code has been detected on the line for a
period of 48 milliseconds. If 1 - unmasked, 0 - masked.
3
1SECIM One Second Status Interrupt Mask. When unmasked an interrupt is initiated when the
1SEC status bit (page 3 address 12H bit 7) goes from low to high. If 1 - unmasked, 0 -
masked.
2
5SECIM Five Second Status Interrupt Mask. When unmasked an interrupt is initiated when the 5
SEC status bit goes from low to high. If 1 - unmasked, 0 - masked.
1
BIOMIM Bit Oriented Message Interrupt Mask. When unmasked an interrupt is initiated when a
pattern 111111110xxxxxx0 has been received on the FDL that is different from the last
message. The new message must persist for 8 out the last 10 message positions to be
accepted as a valid new message. If 1- unmasked, 0 - masked.
0
SIGIM signaling Interrupt Mask. When unmasked an interrupt will be initiated when a change of
state (optionally debounced - see DBEn in the Data Link, signaling Control Word page 1
address 12H) is detected in the signaling bits (AB or ABCD) pattern. If 1 - unmasked, 0 -
masked.
Table 34 - Interrupt Mask Word Three (T1)
(Page 1, Address 1EH)
67