MT9076 Datasheet, PDF (15/160 Pages) Mitel Networks Corporation – T1/E1/J1 3.3V Single Chip Transceiver

Preliminary Information
MT9076
Maskable Interrupts
T1/J1 Mode
E1 Mode
HDLC Interrupts
• Change of state of terminal
synchronization
• Change of state of multiframe
synchronization
• Change of received bit
oriented message
• Change of state of reception
of AIS
• Change of state of reception
of LOS
• Reception of a severely
errored frame
• Change of state of basic
frame alignment
• Change of state of multiframe
synchronization
• Change of state of CRC-4
multiframe synchronization
• Change of state of reception
of AIS
• Change of state of reception
of LOS
• Reception of consecutively
errored FASs
• Go ahead pattern received
• End of packet received
• End of packet transmitted
• End of packet read from
receive FIFO
• Transmit FIFO low
• Frame abort received
• Transmit FIFO underrun
• Receive FIFO full
• Receive FIFO overflow
• Transmit slip
• Receive slip
• Receive framing bit error
• Receive CRC-6 error
• Receive yellow alarm
• Change of receive frame
alignment
• Receive remote signaling
multiframe alarm
• Receive slip
• Receive FAS error
• Receive CRC-4 error
• Receive E-bit
• Receive AIS in timeslot 16
• Receive line code violation • Line code violation
• Receive PRBS error
• Receive PRBS error
• Pulse density violation
• Receive auxiliary pattern
• Framing bit error counter
• Receive RAI
overflow
• FAS error counter overflow
• CRC-6 error counter overflow _{• CRC-4 error counter overflow}
• Out of frame alignment
counter overflow
• Out of frame alignment
counter overflow
• Change of frame alignment
counter overflow
• Receive E-bit counter
overflow
• Line code violation counter
overflow
• Line code violation counter
overflow
• PRBS error counter overflow _{• PRBS error counter overflow}
• PRBS multiframe counter
overflow
• PRBS multiframe counter
overflow
• Multiframes out of alignment _{• Change of state of any Sa bit}
counter overflow
or Sa nibble
• Loop code detected
• Jitter attenuator within 4 bits
• One second timer
of overflow/underflow
• Five second timer
• One second timer
• Receive new bit oriented
message (debounced)
• Signaling (AB or ABCD) bit
change
• Two second timer
• Signaling (CAS) bit change
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