MT9076 Datasheet, PDF (42/160 Pages) Mitel Networks Corporation – T1/E1/J1 3.3V Single Chip Transceiver

MT9076
Preliminary Information
the TX FIFO. The Transmit Byte Count Registers may also be used to tag an end of packet. The total packet
size may be programmed to be up to 65,535 bytes. For a packet length of 1 to 255 bytes it is only necessary to
write the packet size into the Lower Transmit Byte Count Register. For a packet length of 256 to 65,535 bytes it
is necessary to write the 16 bit binary count into the Extended Transmit Byte Count Register (MSByte) and the
Lower Transmit Byte Count Register (LSByte). Note that the order of writing the upper byte before the lower
byte must be observed even when the lower byte is all zero. Internal registers are loaded with the number of
bytes in the packet and decremented after every write to the Tx FIFO. When a count of one is reached, the next
byte written to the FIFO is tagged as an end of packet. The register may be made to cycle through the same
count if the packets are of the same length by setting Control Register 2 bit Cycle.
If the transmitter is in the Idle Channel state when data is written to the Tx FIFO, then an opening flag is sent
and data from Tx FIFO follows. Otherwise, data bytes are transmitted as soon as the current flag byte has been
sent. Tx FIFO data bytes are continuously transmitted until either the FIFO is empty or an EOP or FA status bit
is read by the transmitter. After the last bit of the EOP byte has been transmitted, a 16-bit FCS is sent followed
by a closing flag. When multiple packets of data are loaded into Tx FIFO, only one flag is sent between
packets.
Frame aborts (the transmission of 7F hex), are transmitted by tagging a byte previously written to the Tx FIFO.
When a byte has an FA tag, then an FA is sent instead of that tagged byte. That is, all bytes previous to but not
including that byte are sent. After a Frame Abort, the transmitter returns to the Mark Idle or Interframe Time Fill
state, depending on the state of the Mark idle control bit.
Tx FIFO underrun will occur if the FIFO empties and the last byte did not have either an EOP or FA tag. A
frame abort sequence will be sent when an underrun occurs.
Below is an example of the transmission of a three byte packet (’AA’ ’03’ ’77’ hex) (Interframe time fill). TXcen
can be enabled before or after this sequence.
(a) Write ’04’hex to Control Register 1
-Mark idle bit set
(b) Write ’AA’ hex to TX FIFO
-Data byte
(c) Write ’03’hex to TX FIFO
-Data byte
(d) Write ’34’hex to Control Register 1
-TXEN; EOP; Mark idle bits set
(e) Write ’77’hex to TX FIFO
-Final data byte
The transmitter may be enabled independently of the receiver. This is done by setting the TXEN bit of the
Control Register. Enabling happens immediately upon writing to the register. Disabling using TXen will occur
after the completion of the transmission of the present packet; the contents of the FIFO are not cleared.
Disabling will consist of stopping the transmitter clock. The Status and Interrupt Registers may still be read and
the FIFO and Control Registers may be written to while the transmitter is disabled. The transmitted FCS may
be inhibited using the Tcrci bit of Control Register 2. In this mode the opening flag followed by the data and
closing flag is sent and zero insertion still included, but no CRC. That is, the FCS is injected by the
microprocessor as part of the data field. This is used in V.120 terminal adaptation for synchronous protocol
sensitive UI frames.
8.3.2 HDLC Receiver
After initialization and enabling, the receiver clocks in serial data, continuously checking for Go-aheads (0 1111
1110), flags (0111 1110), and Idle Channel states (at least fifteen ones). When a flag is detected, the receiver
synchronizes itself to the serial stream of data bits, automatically calculating the FCS. If the data length
between flags after zero removal is less than 25 bits, then the packet is ignored so no bytes are loaded into Rx
FIFO. When the data length after zero removal is between 25 and 31 bits, a first byte and bad FCS code are
loaded into the Rx FIFO (see definition of RQ8 and RQ9 below). For an error-free packet, the result in the CRC
register should match the HEX pattern of’F0B8’ when a closing flag is detected.
If address recognition is required, the Receiver Address Recognition Registers are loaded with the desired
address and the Adrec bit in the Control Register 1 is set high. Bit 0 of the Address Registers is used as an
enable bit for that byte, thus allowing either or both of the first two bytes to be compared to the expected values.
Bit 0 of the first byte of the address received (address extension bit) will be monitored to determine if a single or
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