AX250-PQ208I Datasheet, PDF (9/262 Pages) Microsemi Corporation – Axcelerator Family FPGAs

Axcelerator Family FPGAs
Two C-cells, a single R-cell, two Transmit (TX), and two Receive (RX) routing buffers form a Cluster,
while two Clusters comprise a SuperCluster (Figure 1-4). Each SuperCluster also contains an
independent Buffer (B) module, which supports buffer insertion on high-fanout nets by the place-and-
route tool, minimizing system delays while improving logic utilization.
TX TX
TX TX
CC R
CCR
RX RX B RX RX
Figure 1-4 • AX SuperCluster
The logic modules within the SuperCluster are arranged so that two combinatorial modules are side-by-
side, giving a C–C–R – C–C–R pattern to the SuperCluster. This C–C–R pattern enables efficient
implementation (minimum delay) of two-bit carry logic for improved arithmetic performance (Figure 1-5
on page 1-3).
FCI
C-Cell
Y
C-Cell
DCOUT
Y
Carry Logic
FCO
Figure 1-5 • AX 2-Bit Carry Logic
The AX architecture is fully fracturable, meaning that if one or more of the logic modules in a
SuperCluster are used by a particular signal path, the other logic modules are still available for use by
other paths.
At the chip level, SuperClusters are organized into core tiles, which are arrayed to build up the full chip.
For example, the AX1000 is composed of a 3x3 array of nine core tiles. Surrounding the array of core
tiles are blocks of I/O Clusters and the I/O bank ring (Table 1-1). Each core tile consists of an array of 336
SuperClusters and four SRAM blocks (176 SuperClusters and three SRAM blocks for the AX250).
Table 1-1 • Number of Core Tiles per Device
Device
Number of Core Tiles
AX125
1 regular tile
AX250
4 smaller tiles
AX500
4 regular tiles
AX1000
9 regular tiles
AX2000
16 regular tiles
Revision 18
1-3