AX250-PQ208I Datasheet, PDF (74/262 Pages) Microsemi Corporation – Axcelerator Family FPGAs

Detailed Specifications
Buffer Module
Introduction
An additional resource inside each SuperCluster is the Buffer (B) module (Figure 1-4 on page 1-3). When
a fanout constraint is applied to a design, the synthesis tool inserts buffers as needed. The buffer module
has been added to the AX architecture to avoid logic duplication resulting from the hard fanout
constraints. The router utilizes this logic resource to save area and reduce loading and delays on
medium-to-high-fanout nets.
Timing Models and Waveforms
IN
OUT
Figure 2-33 • Buffer Module Timing Model
IN
OUT
GND
VCCA
50%
50%
VCCA
50%
t_BFPD
GND
50%
t_BFPD
Figure 2-34 • Buffer Module Waveform
Timing Characteristics
Table 2-64 • Buffer Module
Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J = 70°C
–2 Speed
–1 Speed
Std Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
Buffer Module Propagation Delays
t_BFPD
Any input to output Y
0.12
0.14
0.16 ns
2-60
Revision 18