AX250-PQ208I Datasheet, PDF (29/262 Pages) Microsemi Corporation – Axcelerator Family FPGAs

Axcelerator Family FPGAs
Table 2-13 summarizes the different combinations of voltages and I/O standards that can be used
together in the same I/O bank.
Table 2-13 • Legal I/O Usage Matrix
I/O Standard
LVTTL 3.3 V (VREF=1.0 V)
3^{– – –}33 ^{– – – – –} 3
LVTTL 3.3 V(VREF=1.5 V)
3^{– – –}3 ^{– – – –}3^– 3
LVCMOS 2.5 V (VREF=1.0 V)
–₃– – – – ₃ – – –₃ –
LVCMOS 2.5 V (VREF=1.25V)
–₃– – – – – – ₃–₃ –
LVCMOS1.8 V
– –₃– – – – – – – – –
LVCMOS1.5 V (VREF = 1.75 V) (JESD8-11) – – – ₃ – – – ₃ – – – –
3.3 V PCI/PCI-X (VREF = 1.0 V)
3^{– – –}33 ^{– – – – –} 3
3.3 V PCI/PCI-X (VREF= 1.5 V)
3^{– – –}3 ^{– – – –}3^– 3
GTL + (3.3 V)
3^{– – –}33 ^{– – – – –} 3
GTL + (2.5 V)
–₃– – – – ₃ – – – – –
HSTL Class I
– – –₃– – – ₃ – – – –
SSTL2 Class I & II
–₃– – – – – – ₃–₃ –
SSTL3 Class I & II
3^{– – –}3 ^{– – – –}3^– 3
LVDS (VREF = 1.0 V)
–₃– – – – ₃ – – –₃ –
LVDS (VREF = 1.25 V)
–₃– – – – – – ₃–₃ –
LVPECL (VREF = 1.0 V)
3^{– – –}33 ^{– – – – –} 3
LVPECL (VREF = 1.5 V)
3^{– – –}3 ^{– – – –}3^– 3
Notes:
1. Note that GTL+ 2.5 V is not supported across the full military temperature range.
2. A "✓" indicates whether standards can be used within a bank at the same time.
Examples:
a) LVTTL can be used with 3.3V PCI and GTL+ (3.3V), when V_REF = 1.0V (GTL+ requirement).
b) LVTTL can be used with 3.3V PCI and SSTL3 Class I and II, when V_REF = 1.5V (SSTL3 requirement).
Note that two I/O standards are compatible if:
• Their VCCI values are identical.
• Their VREF standards are identical (if applicable).
For example, if LVTTL 3.3 V (VREF= 1.0 V) is used, then the other available (i.e. compatible) I/O
standards in the same bank are LVTTL 3.3 V PCI/PCI-X, GTL+, and LVPECL.
Also note that when multiple I/O standards are used within a bank, the voltage tolerance will be limited to
the minimum tolerance of all I/O standards used in the bank.
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