AX250-PQ208I Datasheet, PDF (43/262 Pages) Microsemi Corporation – Axcelerator Family FPGAs

Axcelerator Family FPGAs
Table 2-22 • 3.3 V LVTTL I/O Module
Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J = 70°C (continued)
–2 Speed –1 Speed Std Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
LVTTL Output Drive Strength = 4 (24 mA) / Low Slew Rate
t_DP
t_PY
t_ENZL
Input Buffer
Output Buffer
Enable to Pad Delay through the Output Buffer—Z to
Low
1.68
10.45
10.61
1.92
11.90
12.08
2.26 ns
13.99 ns
14.21 ns
t_ENZH
Enable to Pad Delay through the Output Buffer—Z to
High
10.47
11.93
14.02 ns
t_ENLZ
Enable to Pad Delay through the Output Buffer—Low
1.92
1.94
1.94 ns
to Z
t_ENHZ
Enable to Pad Delay through the Output Buffer—High
2.57
2.58
2.59 ns
to Z
t_IOCLKQ
Sequential Clock-to-Q for the I/O Input Register
0.67
0.77
0.90 ns
t_IOCLKY
Clock-to-output Y for the I/O Output Register and the
0.67
0.77
0.90 ns
I/O Enable Register
t_SUD
t_SUE
t_HD
t_HE
t_CPWHL
t_CPWLH
t_WASYN
t_REASYN
t_HASYN
t_CLR
t_PRESET
Data Input Set-Up
Enable Input Set-Up
Data Input Hold
Enable Input Hold
Clock Pulse Width High to Low
Clock Pulse Width Low to High
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Removal Time
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
0.23
0.27
0.31 ns
0.26
0.30
0.35 ns
0.00
0.00
0.00 ns
0.00
0.00
0.00 ns
0.39
0.39
0.39
ns
0.39
0.39
0.39
ns
0.37
0.37
0.37
ns
0.13
0.15
0.17 ns
0.00
0.00
0.00 ns
0.23
0.27
0.31 ns
0.23
0.27
0.31 ns
Revision 18
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