A3PE1500-2FG676 Datasheet, PDF (83/164 Pages) Microsemi Corporation – ProASIC3E Flash Family FPGAs

ProASIC3E Flash Family FPGAs
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-98 • ProASIC3E CCC/PLL Specification
Parameter
Minimum
Typical
Maximum
Units
Clock Conditioning Circuitry Input Frequency f_{IN_CCC}
Clock Conditioning Circuitry Output Frequency f_{OUT_CCC}
Delay Increments in Programmable Delay Blocks ^{1, 2}
Serial Clock (SCLK) for Dynamic PLL⁴
1.5
0.75
160³
350
MHz
350
MHz
ps
125
MHz
Number of Programmable Values in Each
32
Programmable Delay Block
Input Period Jitter
1.5
ns
CCC Output Peak-to-Peak Period Jitter F_{CCC_OUT}
Max Peak-to-Peak Period Jitter
1 Global
Network Used
3 Global
Networks Used
0.75 MHz to 24 MHz
0.50%
0.70%
24 MHz to 100 MHz
1.00%
1.20%
100 MHz to 250 MHz
1.75%
2.00%
250 MHz to 350 MHz
2.50%
5.60%
Acquisition Time
LockControl = 0
300
µs
Tracking Jitter ⁵
LockControl = 1
LockControl = 0
6.0
ms
1.6
ns
LockControl = 1
0.8
ns
Output Duty Cycle
48.5
Delay Range in Block: Programmable Delay 1 ^{1, 2}
0.6
51.5
%
5.56
ns
Delay Range in Block: Programmable Delay 2 ^1,2
Delay Range in Block: Fixed Delay^1,4
0.025
2.2
5.56
ns
ns
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings
2. T_J = 25°C, VCC = 1.5 V.
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to SmartGen online help for more information.
4. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
Revision 12
2- 69