A3PE1500-2FG676 Datasheet, PDF (38/164 Pages) Microsemi Corporation – ProASIC3E Flash Family FPGAs

ProASIC3E DC and Switching Characteristics
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is
supported as part of the 3.3 V LVTTL support.
Table 2-25 • Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL VOH IOL IOH IOSL
IOSH IIL¹ IIH²
Min.
Drive Strength V
Max. Min., Max.
V
V
V
Max.
V
Min.
V mA mA
Max.
mA³
Max.
mA³
µA⁴ µA⁴
4 mA
–0.3 0.8
2
3.6
0.4
2.4 4 4
27
25
10 10
8 mA
–0.3 0.8
2
3.6
0.4
2.4 8 8
54
51
10 10
12 mA
–0.3 0.8
2
3.6
0.4
2.4 12 12
109
103
10 10
16 mA
–0.3 0.8
2
3.6
0.4
2.4 16 16
127
132
10 10
24 mA
–0.3 0.8
2
3.6
0.4
2.4 24 24
181
268
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V< VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN< VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Test Point
Datapath
35 pF
R=1k
Test Point
Enable Path
R to VCCI for t_LZ / t_ZL / t_ZLS
R to GND for t_HZ / t_ZH / t_ZHS
35 pF for t_ZH / t_ZHS / t_ZL / t_ZLS
35 pF for t_HZ / t_LZ
Figure 2-6 • AC Loading
Table 2-26 • 3.3 V LVTTL / 3.3 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
0
Input High (V)
3.3
Measuring Point* (V)
1.4
VREF (typ.) (V)
–
C_LOAD (pF)
35
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
2-24
Revision 12