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| A3PE1500-2FG676 Datasheet, PDF (72/164 Pages) Microsemi Corporation – ProASIC3E Flash Family FPGAs | |||
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ProASIC3E DC and Switching Characteristics
Output Enable Register
CLK
D_Enable
50%
1
50%
tOESUD tOEHD
50% 0 50%
50%
50%
tOECKMPWH tOECKMPWL
50%
50%
50%
Enable
Preset
Clear
EOUT
50%
tOESUEtOEHE
tOEWPRE
50%
tOERECPRE
50%
tOEWCLR tOERECCLR
50%
50%
tOEPRE2Q
50% 50%
tOECLKQ
tOECLR2Q
50%
tOEREMPRE
50%
tOEREMCLR
50%
Figure 2-29 ⢠Output Enable Register Timing Diagram
Timing Characteristics
Table 2-88 ⢠Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
â2 â1 Std. Units
tOECLKQ
Clock-to-Q of the Output Enable Register
0.59 0.67 0.79 ns
tOESUD
Data Setup Time for the Output Enable Register
0.31 0.36 0.42 ns
tOEHD
Data Hold Time for the Output Enable Register
0.00 0.00 0.00 ns
tOESUE
Enable Setup Time for the Output Enable Register
0.44 0.50 0.58 ns
tOEHE
Enable Hold Time for the Output Enable Register
0.00 0.00 0.00 ns
tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register
0.67 0.76 0.89 ns
tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register
0.67 0.76 0.89 ns
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register
0.00 0.00 0.00 ns
tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register
0.22 0.25 0.30 ns
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register
0.00 0.00 0.00 ns
tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register
0.22 0.25 0.30 ns
tOEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 ns
tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 ns
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
0.36 0.41 0.48 ns
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register
0.32 0.37 0.43 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-58
Revision 12
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