A3PE1500-2FG676 Datasheet, PDF(24/164 Page) Microsemi Corporation

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A3PE1500-2FG676 Datasheet, PDF (24/164 Pages) Microsemi Corporation – ProASIC3E Flash Family FPGAs

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ProASIC3E DC and Switching Characteristics

Combinatorial Cells ContributionâPC-CELL

PC-CELL = NC-CELL* ï¡1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

ï¡1 is the toggle rate of VersaTile outputsâguidelines are provided in Table 2-11 on

page 2-11.

FCLK is the global clock signal frequency.

Routing Net ContributionâPNET

PNET = (NS-CELL + NC-CELL) * ï¡1 / 2 * PAC8 * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

ï¡1 is the toggle rate of VersaTile outputsâguidelines are provided in Table 2-11 on

page 2-11.

FCLK is the global clock signal frequency.

I/O Input Buffer ContributionâPINPUTS

PINPUTS = NINPUTS * ï¡2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

ï¡2 is the I/O buffer toggle rateâguidelines are provided in Table 2-11 on page 2-11.

FCLK is the global clock signal frequency.

I/O Output Buffer ContributionâPOUTPUTS

POUTPUTS = NOUTPUTS * ï¡2 / 2 * ï¢1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

ï¡2 is the I/O buffer toggle rateâguidelines are provided in Table 2-11 on page 2-11.

ï¢1 is the I/O buffer enable rateâguidelines are provided in Table 2-12 on page 2-11.

FCLK is the global clock signal frequency.

RAM ContributionâPMEMORY

ï¢ ï¢ PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

ï¢2 is the RAM enable rate for read operationsâguidelines are provided in Table 2-12 on

page 2-11.

FWRITE-CLOCK is the memory write clock frequency.

ï¢3 is the RAM enable rate for write operationsâguidelines are provided in Table 2-12 on

page 2-11.

PLL ContributionâPPLL

PPLL = PAC13 + PAC14 * FCLKOUT

FCLKOUT is the output clock frequency.1

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the

PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output

clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.

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Revision 12

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