A40MX02-FPL68 Datasheet, PDF (80/142 Pages) Microsemi Corporation – Single-Chip ASIC Alternative, 3,000 to 54,000 System Gates, Up to 2.5 kbits Configurable Dual-Port SRAM

40MX and 42MX FPGA Families
Table 1-38 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed
–F Speed
Parameter / Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Global Clock Network
t_CKH
Input LOW to HIGH FO = 32
2.7
3.0
3.4
4.0
5.6 ns
FO = 635
3.0
3.3
3.8
4.4
6.2 ns
t_CKL
Input HIGH to LOW FO = 32
3.8
4.2
4.8
5.6
7.8 ns
FO = 635
4.9
5.4
6.1
7.2
10.1 ns
t_PWH Minimum Pulse
FO = 32 1.8
2.0
2.2
2.6
3.6
ns
Width HIGH
FO = 635 2.0
2.2
2.5
2.9
4.1
ns
t_PWL
Minimum Pulse
FO = 32 1.8
2.0
2.2
2.6
3.6
ns
Width LOW
FO = 635 2.0
2.2
2.5
2.9
4.1
ns
t_CKSW Maximum Skew
FO = 32
0.8
0.8
0.9
1.0
1.4 ns
FO = 635
0.8
0.8
0.9
1.0
1.4 ns
t_SUEXT Input Latch External FO = 32 0.0
0.0
0.0
0.0
0.0
ns
Set-Up
FO = 635 0.0
0.0
0.0
0.0
0.0
ns
t_HEXT Input Latch External FO = 32 2.8
3.2
3.6
4.2
5.9
ns
Hold
FO = 635 3.3
3.7
4.2
4.9
6.9
ns
t_P
Minimum Period
FO = 32 5.5
6.1
6.6
7.6
12.7
ns
(1/f_MAX)
FO = 635 6.0
6.6
7.2
8.3
13.8
ns
f_MAX
Maximum Datapath FO = 32
180
164
151
131
Frequency
FO = 635
166
151
139
121
79 MHz
73 MHz
TTL Output Module Timing⁵
t_DLH
Data-to-Pad HIGH
2.6
2.8
3.2
3.8
5.3 ns
t_DHL
Data-to-Pad LOW
3.0
3.3
3.7
4.4
6.2 ns
t_ENZH Enable Pad Z to HIGH
2.7
3.0
3.3
3.9
5.5 ns
t_ENZL Enable Pad Z to LOW
3.0
3.3
3.7
4.3
6.1 ns
t_ENHZ Enable Pad HIGH to Z
5.3
5.8
6.6
7.8
10.9 ns
Notes:
1. For dual-module macros, use t_PD1 + t_RD1 + t_PDn, t_CO + t_RD1 + t_PDn, or t_PD1 + t_RD1 + t_SUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1-76
Revision 11