A40MX02-FPL68 Datasheet, PDF (22/142 Pages) Microsemi Corporation – Single-Chip ASIC Alternative, 3,000 to 54,000 System Gates, Up to 2.5 kbits Configurable Dual-Port SRAM

40MX and 42MX FPGA Families
5 V TTL Electrical Specifications
Table 1-9 • 5V TTL Electrical Specifications
Commercial Commercial -F Industrial
Military
Symbol
VOH¹
Parameter Min.
IOH = –10 mA 2.4
Max.
Min.
2.4
Max.
Min. Max.
Min.
Max.
Units
V
IOH = –4 mA
3.7
3.7
V
VOL¹
IOL = 10 mA
0.5
0.5
V
IOL = 6 mA
0.4
0.4
V
VIL
–0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8
V
VIH (40MX)
2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V
VIH (42MX)
2.0 VCCI + 0.3 2.0 VCCI + 0.3 2.0 VCCI + 0.3 2.0 VCCI + 0.3 V
IIL
VIN = 0.5 V
–10
–10
–10
–10
µA
IIH
VIN = 2.7 V
–10
–10
–10
–10
µA
Input Transition
Time, T_R and T_F
C_IO I/O
Capacitance
500
500
500
500
ns
10
10
10
10
pF
Standby Current, A40MX02,
3
25
10
25
mA
ICC²
A40MX04
A42MX09
5
25
25
25
mA
A42MX16
6
25
25
25
mA
A42MX24,
20
25
25
25
mA
A42MX36
Low power mode 42MX devices
0.5
Standby Current only
ICC – 5.0
ICC – 5.0
ICC – 5.0 mA
IIO, I/O source Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)
sink current
Notes:
1. Only one output tested at a time. VCC/VCCI = min.
2. All outputs unloaded. All inputs = VCC/VCCI or GND.
1-18
Revision 11