A40MX02-FPL68 Datasheet, PDF (44/142 Pages) Microsemi Corporation – Single-Chip ASIC Alternative, 3,000 to 54,000 System Gates, Up to 2.5 kbits Configurable Dual-Port SRAM

40MX and 42MX FPGA Families
Timing Characteristics
Table 1-28 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, T_J = 70°C)
–3 Speed –2 Speed –1 Speed
Std Speed
–F Speed
Parameter / Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Logic Module Propagation Delays
t_PD1 Single Module
1.2
1.4
1.6
1.9
2.7 ns
t_PD2 Dual-Module Macros
2.7
3.1
3.5
4.1
5.7 ns
t_CO
Sequential Clock-to-Q
1.2
1.4
1.6
1.9
2.7 ns
t_GO
Latch G-to-Q
1.2
1.4
1.6
1.9
2.7 ns
t_RS
Flip-Flop (Latch) Reset-to-Q
1.2
1.4
1.6
1.9
2.7 ns
Logic Module Predicted Routing Delays1
t_RD1 FO = 1 Routing Delay
t_RD2 FO = 2 Routing Delay
t_RD3 FO = 3 Routing Delay
t_RD4 FO = 4 Routing Delay
t_RD8 FO = 8 Routing Delay
Logic Module Sequential Timing2
1.3
1.5
1.7
2.0
2.8 ns
1.8
2.1
2.4
2.8
3.9 ns
2.3
2.7
3.0
3.6
5.0 ns
2.9
3.3
3.7
4.4
6.1 ns
4.9
5.7
6.5
7.6
10.6 ns
t_SUD
t_HD3
Flip-Flop (Latch)
Data Input Set-Up
Flip-Flop (Latch)
Data Input Hold
3.1
3.5
4.0
4.7
6.6
ns
0.0
0.0
0.0
0.0
0.0
ns
t_SUENA Flip-Flop (Latch)
Enable Set-Up
3.1
3.5
4.0
4.7
6.6
ns
t_HENA Flip-Flop (Latch) Enable Hold 0.0
0.0
0.0
0.0
0.0
ns
t_WCLKA Flip-Flop (Latch)
3.3
3.8
4.3
5.0
7.0
ns
Clock Active Pulse Width
t_WASYN Flip-Flop (Latch)
3.3
3.8
4.3
5.0
7.0
ns
Asynchronous Pulse Width
t_A
f_MAX
Flip-Flop Clock Input Period
Flip-Flop (Latch) Clock
Frequency (FO = 128)
4.8
5.6
6.3
7.5
10.4
ns
181
168
154
134
80 MHz
Input Module Propagation Delays
t_INYH Pad-to-Y HIGH
0.7
0.8
0.9
1.1
1.5 ns
t_INYL Pad-to-Y LOW
0.6
0.7
0.8
1.0
1.3 ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35pF loading.
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Revision 11