PD671XXX-8 Datasheet, PDF (8/14 Pages) Microsemi Corporation – 24-Channel PoE AF and AT DIMM

PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
Pin Description
Signals are categorized as ‘analog’ (input or output) or ‘digital’ (input, output and I/O).
Pin Pin Name Pin Type
Pin Description
Pin
1
85
2
86
3
Vmain
Main V+ input
87
4
88
5
89
6
Power input
90
7
91
8
92
9
Vmain_ret
10
Main V return
93
94
11
95
12
96
13 Port_P0
Channel 1 positive output
97
14 Port_N0
Channel 1 negative output
98
15 Port_P1
Channel 2 positive output
99
16 Port_N1
Channel 2 negative output
100
17 Port_P2
Channel 3 positive output
101
18 Port_N2
Channel 3 negative output
102
19 Port_P3
Channel 4 positive output
103
20 Port_N3
Channel 4 negative output
104
21 Port_P4
Channel 5 positive output
105
22 Port_N4
Channel 5 negative output
106
23 Port_P5
Channel 6 positive output
107
24 Port_N5
Channel 6 negative output
108
25 Port_P6
Analog output Channel 7 positive output
109
26 Port_N6
Channel 7 negative output
100
27 Port_P7
Channel 8 positive output
111
28 Port_N7
Channel 8 negative output
112
29 Port_P8
Channel 9 positive output
113
30 Port_N8
Channel 9 negative output
114
31 Port_P9
Channel 10 positive output 115
32 Port_N9
Channel 10 negative output 116
33 Port_P10
Channel 11 positive output 117
34 Port_N10
Channel 11 negative output 118
35 Port_P11
Channel 12 positive output 119
36
Port_N11
Channel 12 negative output ₁₂₀
37
TBD
TBD
121
38
TBD
TBD
122
39
40
ASICINI_4_
Out
ASICINI_5_
Out
Analog output
Determine DIMM 3 managers
ESPI address
123
124
41 xLed_Cs
Digital output CS for LED support
125
42 TBD
TBD
126
43
BKGD
Digital input Factory use only
127
44
DGND
Ground
Digital ground
128
45
xAsic_Reset Digital I/O
Internal reset to PD69012
129
46
xReset_In
Digital input A reset signal driven by the
Host CPU to PoE DIMM
130
47
ASICINI_0_
Out
Analog output
Determine DIMM 1 manager
ESPI address
131
48
ASICINI_1_
Out
Analog output
Determine DIMM 1 managers
ESPI address
132
49
ASICINI_2_
Out
Analog output
Determine DIMM 2 managers
ESPI address
133
Pin Pin Type
Name
Pin Description
Vmain
Main V+ input
Power input
Vmain_ret
Main V return
Spare
TBD
TBD
TBD
TBD
I2C_Addr_0
Qgnd0
CP_0
ASICINI_6_
Out
ASICINI_7_
Out
xExist
Ext_reg
TBD
TBD
TBD
TBD
Digital input Auto mode; sets I2C address
Ground
Quiet ground
Analog output NC (not in use)
Determine DIMM 4 managers
Analog output ^{ESPI address}
Digital output Grounded internally- DIMM is
present
Analog output External regulation for 3.3 V
3_3Vout
XHswp_On
DGND
SCK
MISO
MOSI
ASICINI_0_
In
ASICINI_1_
In
CS0
Analog output 3.3 V output to support opto
couplers (5 V tolerant)
Digital output Connect to MCU
Ground
Digital ground
Digital I/O SPI clock – PD69012 internal
comm
Digital I/O SPI I/O – PD69012 internal
comm
Digital I/O SPI I/O – PD69012 internal
comm
Analog input Determine DIMM managers
ESPI address
Analog input Determine DIMM managers
ESPI address
Digital I/O CS for ESPI
DGND
Ground
Digital ground
Copyright © 2009
Microsemi
Page 7
Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: [phone], Outside the USA: [phone] Fax: [phone]