PD671XXX-8 Datasheet, PDF (5/14 Pages) Microsemi Corporation – 24-Channel PoE AF and AT DIMM

PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM
Data Sheet (Non-confidential)
Electrical Characteristics _________________________________
The following sections detail the DC and analog characteristics.
DC Characteristics for Digital Inputs and Outputs
PARAMETER
SYMBOL MIN.
MAX. UNIT
REMARKS
Pin Name
Type
High level input voltage
Low level input voltage
Input voltage hysteresis
Input high current
Input low current
Pin Name
Type
High level input voltage
Low level input voltage
Input voltage hysteresis
Input high current
Input low current
High level output voltage
Low level output voltage
Tri state output current
Pin Name
Type
High level input voltage
Low level output voltage
Low level input voltage
Input voltage hysteresis
OFF state output current
SCL, xDisable_Ports, Rx (without internal pull-up/pull-down resistor)
Schmitt Trigger CMOS input, TTL level
V_IH
2.0
V
V_IL
0.8
V
0.3
V
I_IH
-1
+1
μA
I_IL
-1
+1
μA
MOSI, MISO, CS, Tx (without internal pull-up/down resistor)
SCK (with internal resistor)
CMOS I/O, TTL level
V_IH
2.0
V
V_IL
0.8
V
0.3
V
I_IH
-1
+1
μA
I_IL
-1
+1
μA
V_PERI-0.4V
V I_out = 3 mA
0.4
V I_out = 3 mA
-1
+1
μA
xAsic_Reset (with internal resistor)
SDA (without internal resistor)
CMOS open drain output with Schmitt Trigger input, TTL level
V_IH
2.0
V
V_OH
0.4
V I_out = 3mA
V_IL
0.8
V
0.3
V
-1
+1
μA
Electrical Characteristics for Analog I/O Pads
PARAMETER
MIN MAX UNIT
REMARKS
Pin Name
Operating voltage
Pin current consumption
VPORT_POSx
44 62
V
-5 +10 μA
Pin Name
VPORT_NEGx
Operating voltage
0 Vmain V
Pin current consumption
-5 +10 μA
Pin Name
Vmain
Operating voltage – AF mode 40 57
V
Operating voltage – AT mode 50 57
V
V_main current consumption
40 mA
Pin Name
3_3Vout
Voltage
3.13 3.46 V
Output current
6 mA
30 mA
Port driver, Vport measurement and AC generator are
off
Port driver, V_port measurement and AC generator are off
Recommended Range 48v to 55v
Recommended Range 51v to 55v
Total on V_main
Without external NPN (see Q1 in Figure 8)
When using external NPN for V_PERI (see Q1 in Figure 8)
Copyright © 2009
Microsemi
Page 5
Rev. 1.0 / 17-March-10
Analog Mixed Signal Group
2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: [phone], Outside the USA: [phone] Fax: [phone]