A3PE3000-FGG324 Datasheet, PDF (29/162 Pages) Microsemi Corporation – ProASIC3E Flash Family FPGAs with Optional Soft ARM Support

ProASIC3E Flash Family FPGAs
t_EOUT
DQ
E
CLK
t_ZL, t_ZH, t_HZ, t_LZ, t_ZLS, t_ZHS
DQ
D
CLK
EOUT
DOUT
PAD
I/O Interface
D
E
EOUT
PAD
50%
t_{EOUT (R)}
50%
t_ZL
Vtrip
VOL
t_EOUT = MAX(t_EOUT(r), t_EOUT(f))
VCC
50%
t_{EOUT (F)}
50%
t_HZ
90% VCCI
VCC
50%
t_ZH
VCC
VCCI
Vtrip
50%
t_LZ
10% V_CCI
VCC
D
E ^50%
EOUT
PAD
t_{EOUT (R)}
50%
VCC
50%
t_ZLS
Vtrip
VOL
t_{EOUT (F)}
50%
VOH
VCC
50%
t_ZHS
Vtrip
Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)
Revision 13
2- 15