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A3PE3000-FGG324 Datasheet, PDF (27/162 Pages) Microsemi Corporation – ProASIC3E Flash Family FPGAs with Optional Soft ARM Support
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ProASIC3E Flash Family FPGAs
tPY
tDIN
PAD
DQ
Y
DIN
CLK
To Array
tPY = MAX(tPY(R), tPY(F))
tDIN = MAX(tDIN(R), tDIN(F))
VIH
I/O Interface
Vtrip
Vtrip
PAD
VIL
VCC
Y
GND
50%
tPY
(R)
50%
tPY
(F)
tPYS
(R)
tPYS
(F)
DIN
GND
50%
tDIN
(R)
VCC
tDIN
(F)
Figure 2-3 • Input Buffer Timing Model and Delays (example)
50%
Revision 13
2- 13
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