A3PE3000-FGG324 Datasheet, PDF (20/162 Pages) Microsemi Corporation – ProASIC3E Flash Family FPGAs with Optional Soft ARM Support

ProASIC3E DC and Switching Characteristics
Calculating Power Dissipation
Quiescent Supply Current
Table 2-7 • Quiescent Supply Current Characteristics
A3PE600
A3PE1500
A3PE3000
Typical (25°C)
5 mA
12 mA
25 mA
Maximum (Commercial)
30 mA
70 mA
150 mA
Maximum (Industrial)
45 mA
105 mA
225 mA
Notes:
1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in
Table 2-8 and Table 2-9 on page 2-7.
2. –F speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher I/O
leakage.
Power per I/O Pin
Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
VMV
(V)
Static Power
PDC2 (mW)¹
Dynamic Power
PAC9 (µW/MHz)²
Single-Ended
3.3 V LVTTL/LVCMOS
3.3
–
17.39
3.3 V LVTTL/LVCMOS – Schmitt trigger
3.3
3.3 V LVTTL/LVCMOS Wide Range³
3.3
3.3 V LVTTL/LVCMOS Wide Range – Schmitt trigger³
3.3
–
25.51
–
16.34
–
24.49
2.5 V LVCMOS
2.5
–
5.76
2.5 V LVCMOS – Schmitt trigger
2.5
–
7.16
1.8 V LVCMOS
1.8
–
2.72
1.8 V LVCMOS – Schmitt trigger
1.8
–
2.80
1.5 V LVCMOS (JESD8-11)
1.5
–
2.08
1.5 V LVCMOS (JESD8-11) – Schmitt trigger
1.5
–
2.00
3.3 V PCI
3.3
–
18.82
3.3 V PCI – Schmitt trigger
3.3
–
20.12
3.3 V PCI-X
3.3
–
18.82
3.3 V PCI-X – Schmitt trigger
3.3
–
20.12
Voltage-Referenced
3.3 V GTL
3.3
2.90
8.23
2.5 V GTL
2.5
2.13
4.78
3.3 V GTL+
3.3
2.81
4.14
2.5 V GTL+
2.5
2.57
3.71
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
2-6
Revision 13