A3PN015-QNG68 Datasheet, PDF (111/114 Pages) Microsemi Corporation – ProASIC3 nano Flash FPGAs

ProASIC3 nano Flash FPGAs
Revision
Revision 1 (cont’d)
DC and Switching
Characteristics
Advance v0.2
Packaging Advance
v0.2
Changes
Page
The device architecture figures, Figure 1-3 • ProASIC3 nano Device Architecture
Overview with Two I/O Banks (A3PN060 and A3PN125) through Figure 1-4 •
ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250),
were revised. Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O
Banks and No RAM (A3PN010 and A3PN030) is new.
1-3
through
1-4
The "PLL and CCC" section was revised to include information about CCC-GLs in 1-6
A3PN020 and smaller devices.
Table 2-2 • Recommended Operating Conditions 1, 2 was revised to add VMV to 2-2
the VCCI row. The following table note was added: "VMV pins must be connected
to the corresponding VCCI pins."
The values in Table 2-7 • Quiescent Supply Current Characteristics were revised 2-6
for A3PN010, A3PN015, and A3PN020.
A table note, "All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide 2-16, 2-18
range, as specified in the JESD8-B specification," was added to Table 2-14 •
Summary of Maximum and Minimum DC Input and Output Levels, Table 2-18 •
Summary of I/O Timing Characteristics—Software Default Settings (at 35 pF),
and Table 2-19 • Summary of I/O Timing Characteristics—Software Default
Settings (at 10 pF).
3.3 V LVCMOS Wide Range was added to Table 2-21 • I/O Output Buffer 2-19, 2-20
Maximum Resistances 1 and Table 2-23 • I/O Short Currents IOSH/IOSL.
The "48-Pin QFN" pin diagram was revised.
4-2
Note 2 for the "48-Pin QFN", "68-Pin QFN", and "100-Pin VQFP" pin diagrams 4-2, 4-5,
was added/changed to "The die attach paddle of the package is tied to ground 4-9
(GND)."
The "100-Pin VQFP" pin diagram was revised to move the pin IDs to the upper 4-9
left corner instead of the upper right corner.
Revision 11
5-5